MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 71
MC9S08QG8CPBE
Manufacturer Part Number
MC9S08QG8CPBE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QG8CPBE.pdf
(314 pages)
Specifications of MC9S08QG8CPBE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
8KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08QG8CPBE
Manufacturer:
CYPRESS
Quantity:
310
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5.8.3
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
Freescale Semiconductor
BDFR is writable only through serial background debug commands, not from user programs.
Reset:
BDFR
Field
0
W
R
System Background Debug Force Reset Register (SBDFR)
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/ACMPO/BKGD/MS must be high immediately after
issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing
WRITE_BYTE command. See
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
0
0
6
Table 5-5. SBDFR Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
0
0
5
Table A-9., “Control
0
0
4
Description
Timing,” for more information.
Chapter 5 Resets, Interrupts, and General System Control
3
0
0
0
0
2
0
0
1
BDFR
0
0
0
1
69
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