LE3100MICH S L9PU Intel, LE3100MICH S L9PU Datasheet - Page 26

• Manufacturer Part Number: LE3100MICH S L9PU
• Manufacturer: Intel

Specifications of LE3100MICH S L9PU

• Family Name: Xeon Processor 3100
• Device Core Size: 64b
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 1.3625V
• Operating Supply Voltage (min): 0.85V
• Mounting: Surface Mount
• Pin Count: 1284
• Package Type: FCBGA3
• Lead Free Status / RoHS Status: Compliant

2.8
2.8.1
Table 2-14. Core Frequency to FSB Multiplier Configuration
26
2.
3.
4.
Clock Specifications
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
Notes:
1.
2.
Multiplication of System
Core Frequency to FSB
GTLREF is to be generated from V
used on the board (for Quad-Core processors compatibility) the GTLREF lands connected to the Variable
GTLREF circuit may require different resistor values. Each GTLREF land must be connected, refer to the
platform design guide for implementation details.
R
appropriate platform design guide for the board impedance. Refer to processor I/O buffer models for I/V
characteristics.
COMP resistance must be provided on the system board with 1% resistors. See the applicable platform
design guide for implementation details. COMP[3:0] and COMP8 resistors are to V
Individual processors operate only at or below the rated frequency.
Listed frequencies are not necessarily committed production frequencies.
TT
is the on-die termination resistance measured at V
Frequency
1/10.5
1/11.5
1/12.5
1/13.5
1/7.5
1/8.5
1/9.5
1/10
1/11
1/12
1/13
1/14
1/15
1/6
1/7
1/8
1/9
Table 2-14
(333 MHz BCLK/1333 MHz
for the processor supported ratios.
TT
Core Frequency
by a voltage divider of 1% resistors. If a Varibale GTLREF circuit is
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3.16 GHz
3.33 GHz
3.50 GHz
3.66 GHz
3.83 GHz
4.16 GHz
4.33 GHz
4.50 GHz
4.66 GHz
2 GHz
3 GHz
4 GHz
5 GHz
FSB)
TT
/3 of the GTL+ output driver. Refer to the
Notes
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1, 2
Electrical Specifications
SS
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Datasheet