LE3100MICH S L9PU Intel, LE3100MICH S L9PU Datasheet - Page 27
LE3100MICH S L9PU
Manufacturer Part Number
LE3100MICH S L9PU
Description
Manufacturer
Intel
Datasheet
1.LE3100MICH_S_L9PU.pdf
(106 pages)
Specifications of LE3100MICH S L9PU
Family Name
Xeon Processor 3100
Device Core Size
64b
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
1.3625V
Operating Supply Voltage (min)
0.85V
Mounting
Surface Mount
Pin Count
1284
Package Type
FCBGA3
Lead Free Status / RoHS Status
Compliant
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Electrical Specifications
2.8.2
Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0]
2.8.3
2.8.4
Table 2-16. Front Side Bus Differential BCLK Specifications
Datasheet
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]).
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The processor will operate at a 1333 MHz FSB frequency (selected by a 333 MHz
BCLK[1:0] frequency). Individual processors will only operate at their specified FSB
frequency.
For more information about these signals, refer to
platform design guidelines.
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to
platform design guidelines for decoupling and routing guidelines.
BCLK[1:0] Specifications
Notes:
1.
2.
V
CROSS(abs)
Symbol
∆V
V
SWING
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
BSEL2
V
V
CROSS
V
V
OS
US
H
L
H
H
H
H
L
L
L
L
Input Low Voltage
Input High Voltage
Absolute Crossing
Point
Range of Crossing
Points
Overshoot
Undershoot
Differential Output
Swing
Table 2-15
Parameter
BSEL1
H
H
H
H
L
L
L
L
defines the possible combinations of the signals and the
Table 2-3
-0.300
BSEL0
0.300
0.300
-0.30
Min
N/A
N/A
N/A
H
H
H
H
L
L
L
L
for DC specifications. Refer to the appropriate
Typ
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FSB Frequency
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
333 MHz
Section 4.2
0.550
0.140
Max
1.15
N/A
N/A
N/A
1.4
and the appropriate
Unit
V
V
V
V
V
V
V
Figure
2-3
2-3
2-3
2-3
2-3
2-3
2-4
Notes
3
3
2
4
4
5
1
-
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