PPC405EP-3GB200C Applied Micro Circuits Corporation, PPC405EP-3GB200C Datasheet - Page 48

• Manufacturer Part Number: PPC405EP-3GB200C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405EP-3GB200C

• Family Name: 405EP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.65V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 385
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

PPC405EP – PowerPC 405EP Embedded Processor
Table 15. I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I
48
SDRAM Interface
BA1:0
BankSel3:0
CAS
ClkEn0:1
DQM0:3
MemAddr12:00
MemData00:31
RAS
WE
External Slave Peripheral Interface
PerAddr06:31
[PerBLast]
PerCS0
[PerCS1:4]
PerData00:31
PerOE
PerR/W
PerReady
PerWBE0:3
ExtReset
PerClk
command is used by SDRAM.
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
OH
is specified at 2.4V and I
Signal
Setup Time
(T
IS
1.6
6.5
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
4
5
min)
OL
Input (ns)
is specified at 0.4V.
Hold Time
(T
IH
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
1
1
1
1
min)
Valid Delay
(T
OV
4.7
4.5
4.8
4.1
4.7
4.8
4.9
3.8
4.1
6.4
4.1
4.1
4.1
0.4
na
na
4
5
8
max)
Output (ns)
Hold Time
(T
OH
-0.2
1.7
1.6
1.9
2.1
1.2
2.1
1.6
1.5
1.5
1.5
1.6
1.6
na
na
2
2
2
0
min)
(minimum)
Output Current (mA)
15.3
15.3
15.3
28.7
15.3
15.3
15.3
15.3
15.3
15.3
10.3
15.3
10.3
10.3
10.3
15.3
15.3
I
12
na
OH
Revision 1.08 – March 24, 2008
(minimum)
10.2
10.2
10.2
19.3
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
I
7.1
7.1
7.1
7.1
na
OL
8
Data Sheet
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
Clock
Notes
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
AMCC
4