MCIMX31LVKN5C Freescale, MCIMX31LVKN5C Datasheet - Page 65
![no-image](/images/manufacturer_photos/0/2/261/freescale_sml.jpg)
MCIMX31LVKN5C
Manufacturer Part Number
MCIMX31LVKN5C
Description
Manufacturer
Freescale
Datasheet
1.MCIMX31LVKN5C.pdf
(122 pages)
Specifications of MCIMX31LVKN5C
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCIMX31LVKN5C
Manufacturer:
FREESCALE
Quantity:
1 831
Company:
Part Number:
MCIMX31LVKN5C
Manufacturer:
FREESCALE
Quantity:
748
Company:
Part Number:
MCIMX31LVKN5C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31LVKN5C
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MCIMX31LVKN5CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
4.3.15.4 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See
TFT LCD Panels, Electrical
4.3.15.4.1
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively.
interface timing,
Freescale Semiconductor
•
•
•
•
•
IP21
IP22
IP23
IP24
IP25
IP26
ID
The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).
The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It
remains low for a single clock cycle.
The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
— At a transition to an even field (of the same frame), they do not coincide.
The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
and DISPB_D3_HSYNC coincide.
SPL rise time
CLS fall time
CLS rise time
CLS rise and PS fall time
PS rise time
REV toggle time
Table 49. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
Interface to a TV Encoder,
Parameter
Characteristics.”
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Symbol
Tsplr
Tclsr
Tclsf
Tpsf
Tpsr
Trev
Functional Description
(BGXP – 1) * Tdpcp
CLS_RISE_DELAY * Tdpcp
CLS_FALL_DELAY * Tdpcp
PS_FALL_DELAY * Tdpcp
PS_RISE_DELAY * Tdpcp
REV_TOGGLE_DELAY * Tdpcp
Section 4.3.15.2.2, “Interface to Active Matrix
Value
Figure 51
Electrical Characteristics
depicts the
Units
ns
ns
ns
ns
ns
ns
65