EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 37

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Documentation Changes
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Issue:
Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
Intel
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80314 I/O Processor Companion Chip Specification Update
PCI-X Bridge Status Register (Embedded Mode) (PE_PCI/X _S) has incorrect
values for default bus and function numbers
In Section 3.18.4.23, Table 129 shows bus and function numbers for this register with values of
0x00 and 111b respectively. The correct default values are 0xff and 0x0 respectively.
PFAB_CSR Register is described incorrectly
In Section 3.18.5.20, Table 152, the behavior of the SW_RST bit (bit[8]) is incorrectly
documented. The bit does not affect all registers as indicated. The correct behavior for this bit is to
flush the Switch Fabric Network (SFN) buffers.
Removed and moved to Errata #39
Various attribute bits are not correct
The following bits are not documented correctly:
I2C_RD_DATA Register defines incorrect byte order
In Section 9.7.4, Table 448, the I2C_RD_DATA must be defined as follows:
Bits[31:24]—Received I
Bits[23:16]—Received I
Bits[15:8]—Received I
Bits[7:1]—Received I
GPIO offset is not correct
The Intel
following:
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The attributes of bits[15:8] at offset 0x3C of the PCI configuration space are documented as
read-only. They should be read/write.
The attributes of bit[24] at offset 0xE0 of the PCI configuration space are documented as
read/write. They should be read-only.
Bits[15:0] at offset 0xE4 of the PCI configuration space are read-only but can be cleared by
writing all 1s.
GPIO Data Register offset is documented as 0x5A0 (Table 458). It should be 0xA0.
GPIO Control Register offset is documented as 0x5A4 (Table 459). It should 0xA4.
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80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
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80314 I/O Processor Companion Chip Developer’s Manual incorrectly lists the
2
C data, byte 3
2
C data, byte 2
2
2
C data, byte 0
C data, byte 1
Documentation Changes
37