MC94MX21DVKN3 Freescale, MC94MX21DVKN3 Datasheet - Page 29

• Manufacturer Part Number: MC94MX21DVKN3
• Manufacturer: Freescale

Specifications of MC94MX21DVKN3

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.10
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the i.MX21 Reference
Manual.
Freescale Semiconductor
The pixel clock is equal to LCDC_CLK / (PCD + 1).
When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock.
When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width.
The polarity of SCLK and LD can also be programmed.
Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.
Symbol
T1
T2
T3
LCD Controller
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control
Ref No.
Register.
SCLK period
Pixel data setup time
Pixel data up time
1
2
3
4
5
6
7
Table 18. Timing Parameters for
SPI_RDY to SS output low
SS output low to first SCLK edge
Last SCLK edge to SS output high
SS output high to SPI_RDY low
SS output pulse width
SS input low to first SCLK edge
SS input pulse width
LD[17:0]
Parameter
LSCLK
Table 19. LCDC SCLK Timing Parameters
Figure 19. SCLK to LD Timing Diagram
Parameter
MC94MX21 Technical Data, Rev. 1.5
T2
Figure 14
Minimum
Tsclk + WAIT
23
11
11
Minimum
3·Tsclk
T3
2·Tsclk
2T
0
T
T
T1
1
through
2
3.0 ± 0.3V
3
Figure 18
Maximum
–
Maximum
–
–
–
–
–
–
2000
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
Specifications
Unit
ns
ns
ns
29