MC94MX21DVKN3 Freescale, MC94MX21DVKN3 Datasheet - Page 94

• Manufacturer Part Number: MC94MX21DVKN3
• Manufacturer: Freescale

Specifications of MC94MX21DVKN3

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specifications
3.22.3
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time
and setup time based on the following assumptions:
Rising-edge latch data
In most of case, duty cycle is 50 / 50, therefore:
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
94
•
•
•
•
•
•
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
positive duty cycle = 10 / 2 = 5ns
≥ max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
≥ max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
1. HCLK = AHB System Clock, T
Calculation of Pixel Clock Rise/Fall Time
VSYNC
DATA[7:0]
PIXCLK
Number
1
2
3
4
5
6
Figure 84. Sensor Output Data on Pixel Clock Rising Edge
csi_vsync to csi_pixclk
csi_d setup time
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
Table 45. Non-Gated Clock Mode Parameters
CSI Latches Data on Pixel Clock Falling Edge
Parameter
MC94MX21 Technical Data, Rev. 1.
HCLK
1
= Period of HCLK
2
Valid Data
3
Minimum
9 * T
T
T
HCLK
HCLK
1
1
0
HCLK
Valid Data
5
Maximum
HCLK / 2
6
–
–
–
–
–
1
4
Valid Data
Freescale Semiconductor
MHz
Unit
ns
ns
ns
ns
ns