IPSERIALLITE Altera, IPSERIALLITE Datasheet
IPSERIALLITE
Specifications of IPSERIALLITE
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IPSERIALLITE Summary of contents
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... MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com SerialLite MegaCore Function Version: Document Version: 1.1.0 rev. 1 Document Date: August 2005 1.1.0 ...
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... Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U ...
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... About This User Guide ............................................................................. v Revision History ........................................................................................................................................ v How to Contact Altera .............................................................................................................................. v Typographic Conventions ...................................................................................................................... vi Chapter 1. About This MegaCore Function Release Information ............................................................................................................................... 1–1 Device Family Support ......................................................................................................................... 1–1 New in Version 1.1.0 ............................................................................................................................. 1–2 Features ................................................................................................................................................... 1–2 OpenCore Plus Evaluation .............................................................................................................. 1–3 Performance ............................................................................................................................................ 1–4 Chapter 2. Getting Started System Requirements ............................................................................................................................ 2–1 Design Flow ............................................................................................................................................ 2– ...
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... Methodology Overview ........................................................................................................................ 4–2 Configuring the Simulation ................................................................................................................. 4–3 ModelSim Simulator ........................................................................................................................ 4–3 Other Simulators .............................................................................................................................. 4–5 Sending & Receiving Data Tasks ................................................................................................... 4–8 User Packet Data ............................................................................................................................ 4–11 Running a Simulation .................................................................................................................... 4–13 Simulation Pass & Fail Conditions .............................................................................................. 4–14 iv SerialLite MegaCore Function User Guide MegaCore Function Version 1.1.0 Altera Corporation ...
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... All September 2004 1.0.0 How to Contact For the most up-to-date information about Altera Altera world-wide web site at www.altera.com. For technical support on Altera this product www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. Information Type Technical support www ...
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... Active-low signals are denoted by suffix c:\qdesigns\tutorial\chiptrip.gdf SUBDESIGN ), as well as logic function names (e.g., MegaCore Function Version 1.1.0 All Other Locations + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time ftp.altera.com data1 n resetn , e.g Also, sections of an TRI ) are shown in Altera Corporation , ...
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... The warning indicates information that should be read prior to starting or w continuing the procedure or processes r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Altera Corporation Typographic Conventions Meaning Preliminary vii ...
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... Typographic Conventions viii SerialLite MegaCore Function User Guide MegaCore Function Version 1.1.0 Altera Corporation ...
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... Table 1–2. Device Family Support Stratix Other device families Altera Corporation August 2005 1. About This MegaCore provides information about this release of the Altera ® function. Item Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs ...
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... Electricals based on familiar XAUI standard Low protocol overhead and logic usage Low point-to-point transfer latency No inter-frame gaps required Easy-to-use IP Toolbench interface IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators Support for OpenCore ® Plus evaluation MegaCore Function Version 1.1.0 ...
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... The combination of optional capabilities makes the link well-suited to a wide variety of applications intended to support chip-to-chip, board-to-board, and cross-backplane data transfers. OpenCore Plus Evaluation With the free Altera OpenCore Plus evaluation feature, you can perform the following actions: ■ ■ ■ ...
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... Altera Corporation August 2005 f MAX >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 >156 139 >156 145 ...
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... For more information on IP functional simulation models, see the Simulating Altera in Third-Party Simulation Tools chapter in Volume 3 of the Quartus II Handbook. 5. Altera Corporation August 2005 A PC running the Windows NT/2000/XP, Red Hat Linux 7.3 or 8.0, or Red Hat Enterprise Linux 3.0 operating system Sun ...
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... Obtain & Install Before you can start using Altera MegaCore functions, you must obtain the MegaCore files and install them on your computer. Altera MegaCore the SerialLite functions can be installed from the MegaCore IP Library CD-ROM either during or after Quartus II installation, or downloaded individually from MegaCore the Altera web site and installed separately ...
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... Click Download Free Evaluation on the top right of the product description web page. Fill out the registration form and click Submit Request. Read the Altera MegaCore license agreement, turn on the I have read the license agreement check box, and click Proceed to Download Page. ...
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... Contains encrypted lower-level design files. After installing the MegaCore function, you should set a user library in the Quartus II software that points to this directory. This library allows you to access all the necessary MegaCore files. MegaCore Function Version 1.1 Altera Corporation August 2005 ...
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... Getting Started SerialLite This walkthrough explains how to create a SerialLite MegaCore function variation using the Altera SerialLite IP Toolbench and the Quartus II MegaCore software on a PC. When you are finished generating a SerialLite MegaCore function variation, you can incorporate it into your overall Function project. Walkthrough This walkthrough involves the following steps: ■ ...
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... Select the output file type for your design; the wizard supports VHDL and Verilog HDL. Specify a name for the MegaCore function files, <directory name>\<variation name>. the wizard after you have made these settings. MegaCore Function Version 1.1.0 Figure 2–2 on page 2–7 shows Altera Corporation August 2005 ...
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... You can make changes in any order, but if you move through the pages in the order indicated, no setting changes are required for you to revisit a page you have already completed. To parameterize your MegaCore function, follow these steps: Altera Corporation August 2005 Click Next to launch IP Toolbench. Chapter 3, Specifications ...
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... Included on this page are settings for the following: Bit rate ● Lane count ● Signal propagation delay ● Clock configuration ● Lane polarity reversal ● Lane order reversal ● MegaCore Function Version 1.1.0 Figure 2–3). Figure 2–4 on Altera Corporation August 2005 ...
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... Getting Started Figure 2–4. SerialLite MegaCore Function Basic Configuration Page 2. Altera Corporation August 2005 After you choose your settings on the Basic Configuration page, click Next the Data Ports page. This page allows you to select and configure the data ports, as shown in Figure 2–5 on page 2– ...
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... The options on this page depend heavily on whether or not flow control is enabled. Figure 2–6 on page 2–11 options with flow control disabled. The default configuration, used in this walkthrough, uses no flow control. MegaCore Function Version 1.1.0 shows the Altera Corporation August 2005 ...
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... Getting Started Figure 2–6. SerialLite MegaCore Function Atlantic Receive FIFO Buffer Page (Flow Control Disabled) 4. Altera Corporation August 2005 After you choose your settings on the Atlantic Receive FIFO Buffer page, click Next the Advanced Electricals page. This page, shown in Figure 2–7 on page 2– ...
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... The wizard gives you an estimate of the logic used. This is only an estimate, and depends on what else is being instantiated in the Stratix GX device. For an accurate count of resources utilized, you must synthesize the design. Continue with the default configuration and click Finish. MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... To generate an IP functional simulation model for your MegaCore function, follow these steps: 1. Figure 2–8. IP Toolbench—Set Up Simulation 2. Altera Corporation August 2005 You may only use these simulation model output files for simulation purposes and expressly not for synthesis or any other purposes. Using these models for synthesis creates a non-functional design ...
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... If VHDL is selected, your simulation environment must support mixed-language simulation to use the SerialLite testbench does not, generate a second simulation model using Verilog HDL for use with the SerialLite testbench by repeating step 2. Click OK. MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... Getting Started Step 3: Generate To generate your MegaCore function variation, follow these steps: 1. Figure 2–10. IP Toolbench—Generate 2. Altera Corporation August 2005 Click Step 3: Generate in IP Toolbench (see The generation report lists the design files that IP Toolbench creates (see Figure 2–11 on page 2–16). Click Exit. ...
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... Quartus II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor. .html MegaCore function report file. 2–16 SerialLite MegaCore Function User Guide describes IP Toolbench-generated files Description MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... For more information on IP functional simulation models, see the Simulating Altera in Third-Party Simulation Tools chapter in Volume 3 of the Quartus II Handbook. Altera also provides a configurable testbench for use in evaluating the SerialLite MegaCore function. The testbench is described in detail in Chapter 4, SerialLite Altera Corporation August 2005 ...
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... From the Tools menu, select Tcl Scripts to bring up the script browser. In the project directory, select <design name>_constraints.tcl. Click Run. STRATIX_OPTIMIZATION_TECHNIQUE SPEED AUTO_PACKED_REGISTERS_STRATIX OFF MUX_RESTRUCTURE OFF STATE_MACHINE_PROCESSING AUTO FITTER_EFFORT "STANDARD FIT" MegaCore Function Version 1.1.0 . Use this script as a guide MAX Altera Corporation August 2005 ...
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... Altera web site at www.altera.com/licensing and install it on your computer. When you request a license file, Altera e-mails you a license.dat file. If you do not have Internet access, contact your local Altera representative. To install your license, you can either append the license to your license.dat file or you can specify the MegaCore function’ ...
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... Verify the filename in a DOS box command prompt. Altera recommends that you give the file a unique name, for example, <MegaCore name>_license.dat. Run the Quartus II software. Choose License Setup (Tools menu). The Options dialog box opens to the License Setup page ...
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... MegaCore function, and the RENA and RHENA signals ignore attempts to read from the SerialLite MegaCore function. f For more information on OpenCore Plus hardware evaluation, see “OpenCore Plus Evaluation” on page 1–3 Evaluation of Megafunctions on www.altera.com. SerialLite Link The general decisions you must make for your SerialLite MegaCore function are: Configuration ■ ...
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... Gbps 1 2.5 ns Both ends of link use the same clock source (no clock compensation) Test only, no reversal NA (only one lane) Enabled Packet Disabled Disabled Disabled NA (priority data port disabled) Disabled Minimum (16 entries) Low Low 100 Ω 1,000 Disabled Altera Corporation August 2005 ...
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... In particular, the SerialLite protocol specifies a symmetric link. The number of lanes in one direction must match the number of lanes in the other direction. Interface Overview The SerialLite MegaCore function has four interfaces, shown in Figure ■ ■ ■ ■ Altera Corporation August 2005 Figure 3– One or more lanes ...
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... Atlantic interface that allow for regular or priority data. “Status Interface” on page 3–58. MegaCore Function Version 1.1.0 MRESET_N High-Speed Serial Interface Control 3–56. The “Transceiver Settings” on Altera Corporation August 2005 ...
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... For more information on this interface, refer to FS 13: Atlantic Interface, available at www.altera.com. Figure 3–3. Atlantic Interfaces The SerialLite MegaCore function allows you to create one or two data ports: one for regular data and one for priority data. Each of these ports has a full Atlantic interface ...
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... REOP RERR RMTY RDAT RADR Priority Data Port THENA THDAV THSOP THEOP THERR THMTY SerialLite THDAT THADR MegaCore Function RHENA Variation RHDAV RHVAL RHSOP RHEOP RHERR RHMTY RHDAT RHADR MegaCore Function Version 1.1.0 System Logic System Logic Altera Corporation August 2005 ...
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... The logic on either side of the SerialLite link always acts as a master. This document refers to the logic that drives data into the SerialLite MegaCore function or receives data from the SerialLite MegaCore function as the “system logic.” Altera Corporation August 2005 Regular Data Port TENA ...
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... SerialLite MegaCore function to deliver the received is driven by the SerialLite MegaCore function to deliver the received MegaCore Function Version 1.1.0 Table 3–2. The signals [7..0] Altera Corporation August 2005 ...
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... RENA RHENA Altera Corporation August 2005 Description is driven by the system logic to specify the number of empty bytes at the is driven by the SerialLite MegaCore function to specify the number of ...
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... SerialLite MegaCore function to indicate the beginning driven by the SerialLite MegaCore function to indicate the beginning of a MegaCore Function Version 1.1.0 THDAV indicates there is enough THDAV is Altera Corporation August 2005 ...
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... RHERR being received on the priority data port is invalid (only if the retry-on-error feature is not enabled). Altera Corporation August 2005 Description is driven by the system logic to end a packet on the regular data port (packet is driven by the system logic to end a packet on the priority data port. ...
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... Transmit SerialLite MegaCore Function Atlantic Interface Receive Transceiver Status Control 3–8. SerialLite TX_OUT MegaCore Function (Near) RX_IN High-Speed Serial Interface MegaCore Function Version 1.1.0 3–7) always appears at the High-Speed Serial Interface SerialLite RX_IN MegaCore Function (Remote) TX_OUT Altera Corporation August 2005 ...
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... The bandwidth that can be realized by a SerialLite link depends on the following: ■ ■ ■ Altera Corporation August 2005 The transmit lane(s). These are outputs of the SerialLite MegaCore function. Connect these to the SerialLite MegaCore function on the remote end of the link. The width of the bus is equal to the number of lanes specified ...
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... SerialLite MegaCore Function User Guide Figure 3–9). (Table 3–5 Description This is 20 times faster than the system clock, and somewhat faster than the effective data rate, depending on the features selected. MegaCore Function Version 1.1.0 shows the bit rate values). Altera Corporation August 2005 ...
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... In these cases, you can improve bandwidth by making adjustments to improve efficiency. Altera provides a Microsoft Excel-based tool that can help you estimate and improve the efficiency of your SerialLite link. You can find the calculator and Application Note 389: SerialLite MegaCore Function Bandwidth Calculator at www ...
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... MegaCore function wizard, as shown in Figure 3–11. Aggregate Bit Rate 3–16 SerialLite MegaCore Function User Guide PLL (x20) SerialLite MegaCore Function Atlantic Interface High-Speed Serial Interface MegaCore Function Version 1.1.0 Bit Rate (= 20 X System Clock Rate) Figure 3–11. Altera Corporation August 2005 ...
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... Table 3–7. Frequency Adjustment Options Enabled Disabled Altera Corporation August 2005 shows the allowed lane count values. Description The number of lanes that are instantiated in the SerialLite MegaCore function variation. ...
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... Figure 3–12. Signal Propagation Delay Table 3–8 Table 3–8. Signal Propagation Delay Values Minimum Maximum Default 3–18 SerialLite MegaCore Function User Guide 3–12. shows the allowed signal propagation delay values. 0 N/A 2.5 The signal delay, in nanoseconds. MegaCore Function Version 1.1.0 Description Altera Corporation August 2005 ...
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... Figure one domain to the other. Depending on the relationship between the system clock and the recovered clock, compensation may be required to ensure that no data is lost due to a frequency mismatch. Altera Corporation August 2005 summarizes the different ways you can change the bandwidth Setting Specifies the rate at which bits are sent on the high-speed serial interface. Equal to 20× ...
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... SerialLite MegaCore Function User Guide System Clock Recovered Clock PLL Buffer Recovered Clock Domain Figure 3–14). Because both ends of the link use the same clock source, MegaCore Function Version 1.1.0 Atlantic Interface SerialLite MegaCore Function FPGA System Clock Domain Altera Corporation August 2005 ...
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... If you are using this configuration, select the Near end and far end use different crystals option in the Clock Configuration portion of the wizard. Altera Corporation August 2005 System Clock PLL ...
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... Used when the clock sources for the two ends of the link are independent, but of the same nominal frequency. Clock compensation is implemented. MegaCore Function Version 1.1.0 Atlantic Interface SerialLite MegaCore Function FPGA 2 Tables 3–10 and 3–11 show Description Altera Corporation August 2005 ...
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... MegaCore function. Instead, implement one of the following clocking options: ■ ■ Altera Corporation August 2005 A clock compensation sequence is automatically inserted into the serial stream every 1667 clock cycles. Available only if the Near end and far end use different crystals setting has been selected for clock configuration ...
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... User Logic RX_ANALOGRESET CLK SerialLite MegaCore Function Reset State Machine PLL_ARESET RX_ANALOGRESET CLK User Logic Clock Global Clock Pin MegaCore Function Version 1.1.0 Unused Transceiver ALTGXB Transceiver TX PLL REFCLKB ALTGXB Transceiver TX PLL REFCLKB ALTGXB Transceiver TX PLL REFCLKB Altera Corporation August 2005 ...
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... SerialLite logic implementation size configure the link to detect lane polarity errors but not to reverse the logic, select the Test only option for Lane Polarity in the Link Start-Up portion of the Parameterize - SerialLite MegaCore function wizard. This is the default selection. Altera Corporation August 2005 + - + - If reversal is not selected, and if the link detects that the polarity is incorrect, a catastrophic error is declared ...
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... Reversed polarity is corrected at the receiver. Figures 3–20 and 3–21). The SerialLite logic always Lane 0 Lane 1 Lane 2 Lane 3 Lane 0 Lane 1 Lane 2 Lane 3 MegaCore Function Version 1.1.0 shows the lane polarity Description Lane 0 Lane 1 Lane 2 Lane 3 Lane 3 Lane 2 Lane 1 Lane 0 Altera Corporation August 2005 ...
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... The SerialLite MegaCore function provides two ports: a regular data port and a priority data port. The ports operate differently, and have different strengths. You can use one or the other or both ports. At least one of the two must be used. Altera Corporation August 2005 Figure 3–22, the receiving end cannot unscramble it, and a “ ...
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... This is the default setting. Does not create the signals and logic required to support a regular data port. If this option is chosen, then a priority data port must be created. MegaCore Function Version 1.1.0 Description Table 3–15 shows the regular data Description Altera Corporation August 2005 ...
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... The regular data port allows data to be formatted as a stream or in packets. Streaming data has no beginning or end. It represents an unending sequence of data bytes. Packets of data, by contrast, have a Altera Corporation August 2005 Certain data packets have higher priority than other data You want to use the retry-on-error feature ...
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... The regular data port expects data to be streaming. The TSOP TEOP TMTY RMTY[] RADD[] , the Atlantic interface. MegaCore Function Version 1.1.0 Description TSOP TEOP at the beginning and TADD[] TERR RSOP REOP , , , , RERR , and signals are not available on Altera Corporation August 2005 at , ...
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... FPGA. shows the allowed size values for priority data packets. Altera Corporation August 2005 The SerialLite MegaCore function does not perform any partitioning or reassembly of packets. System logic must ...
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... The size, in bytes, of the largest priority packet that is allowed in the SerialLite implementation being created. Packets are not required to be this size, and may be smaller. Only available if the priority data port has been enabled. MegaCore Function Version 1.1.0 Description Altera Corporation August 2005 ...
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... Once a packet for one channel has started, that packet must be completed before a new packet for a different channel can be started. Packets on the priority data port still interrupt packets on the regular data port, regardless of channel multiplexing. Altera Corporation August 2005 Description Logic is created to test incoming data for oversize packets. Oversize packets are discarded ...
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... This is shown in Chip 2 Atlantic Interface SerialLite SerialLite MegaCore MegaCore Function Function High-Speed Serial Interface MegaCore Function Version 1.1.0 Figure 3–24. System Logic Channel 1 Destination RDAT Channel 2 (RHDAT) Destination RADR (RHADR) Channel n Destination Read Channel Number, Demultiplex Altera Corporation August 2005 ...
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... Table 3–20. Channel Multiplexing Options Enabled Disabled Table 3–21 Table 3–21. Regular Data Channel Count Values Minimum Altera Corporation August 2005 6 ). Table 3–20 Option If selected for the regular data port, created, and a number of channels from 2 to 256 can be specified ...
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... For example TADR channels are specified, then the RADR and buses are 4 bits wide. Only available if channel multiplexing is enabled on the priority data port Altera Corporation August 2005 ...
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... CRC logic is created. CRC usage is specified independently for each port. Disabled CRC logic is not created. CRC usage is specified independently for each port. This is the default CRC setting. Altera Corporation August 2005 Because of the 256-byte packet size limitation, CRC-32 is never really needed on the priority data port (although it is available). ...
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... This feature is only available on the priority data port. It provides for packets with errors to be resent so that only good packets are delivered to the Atlantic receive interface. 3–38 SerialLite MegaCore Function User Guide Description Description MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... Altera Corporation August 2005 When the receiver receives a good packet, the packet is delivered to the Atlantic interface and an ACK acknowledgment is sent back to the transmitter. Any data errors cause the packet to be acknowledged bad (NACK). Once that happens, the receiver ignores all incoming data until it receives the resent packet ...
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... Transmitter Receiver Receive Send ACK ACK Receive NACK Timeout Expires MegaCore Function Version 1.1.0 Receive Packet Good Bad, Out of Order No Send Already NACK NACKed? Altera Corporation August 2005 ...
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... Adding a few clock cycles of margin to the minimum timeout is generally sufficient to ensure robust operation. The maximum total timeout is 2 cycles. Altera Corporation August 2005 shows the retry-on-error options for the priority data port. Option Logic is created to acknowledge packets and resend packets when errors occur ...
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... Flow control is only needed when the system logic on the receiving end of the link is reading the data more slowly than the system logic on the transmitting end of the link is sending data. “Error Handling” on page 3–54. MegaCore Function Version 1.1.0 Description Altera Corporation August 2005 ...
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... PAUSE instruction is issued. The chances are extremely remote that both PAUSE instructions would be corrupted (unless there was something seriously wrong with the link). Altera Corporation August 2005 shows the flow control options. Option Logic is created to implement flow control ...
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... FIFO buffer or the priority data port receive FIFO buffer breaches a threshold. Available only if flow control is enabled and both data ports are enabled. This is the default setting if both data ports are enabled. MegaCore Function Version 1.1.0 Description PAUSE instruction. Available only Description Altera Corporation August 2005 ...
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... The minimum FIFO buffer size depends on a number of factors, but the maximum FIFO buffer size theoretically allowed is 2 practical maximum is determined by the device resources available. Altera Corporation August 2005 shows the flow control pause values. Maximum ...
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... The use of CRC affects latency, which impacts FIFO buffer size if flow control is enabled. This setting affects whether CRC can be utilized, which in turn affects latency. (Figure 3–27). When flow control is used, the FIFO buffer is (Figure 3–28 and Figure MegaCore Function Version 1.1.0 “Optimizing Against Starvation” 3–29). Altera Corporation August 2005 ...
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... Specifications Figure 3–27. FIFO Buffer Structure (Flow Control Not Enabled) Figure 3–28. FIFO Buffer Structure (Flow Control Enabled Without Backup Pause) Altera Corporation August 2005 Width set automatically Headroom Primary Flow Control Threshold Threshold Width set automatically MegaCore Function Version 1.1.0 ...
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... FIFO buffer. 3–48 SerialLite MegaCore Function User Guide Backup Threshold Primary Flow Control Threshold Threshold Width set automatically MegaCore Function Version 1.1.0 Depth set in SerialLite wizard Depth set in SerialLite wizard Figure 3–29). Altera Corporation August 2005 ...
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... Table 3–34. Regular Data Receive FIFO Buffer Size Values (No Flow Control) Minimum Maximum Default Altera Corporation August 2005 (Figure Table 3–35). However, you should pick a reasonable number to avoid Description Determines the number of entries that are built into the regular data receive FIFO buffer. Available only if the regular data has been enabled. ...
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... Table 3–36).The number of entries required for this Figure 3–30 on page MegaCore Function Version 1.1.0 Table 3–37). The number 3–53). Altera Corporation August 2005 ...
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... The FIFO buffer is therefore “starved,” since it has room for more data but data transmission is still suspended. This is wasteful of bandwidth, since the link is idle for no reason. Altera Corporation August 2005 Description The number of priority data receive FIFO buffer entries beyond the required minimum that are provided in the priority data receive FIFO buffer ...
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... This is the default setting. The FIFO buffer threshold sizing is not increased to avoid starvation during flow control. Available only if flow control is enabled. 3–39). There is no theoretical limit to the number of packets that can MegaCore Function Version 1.1.0 Figure 3–31). Description Altera Corporation August 2005 ...
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... FIFO buffer that the packet size has no impact. Figure 3–30. FIFO Buffer Sizing (Flow Control Without Starvation Option) Altera Corporation August 2005 Description Ensures that the FIFO buffer (if flow control is disabled) or the FIFO buffer threshold (if flow control is enabled) is large enough to hold the specified number of packets ...
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... Error Types The SerialLite MegaCore function has three levels of error: ■ ■ ■ 3–54 SerialLite MegaCore Function User Guide Data error Link error Catastrophic error MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... Specifications The causes and results of these errors are summarized in Table 3–40. Error Causes & Results Error Type Data Link Catastrophic Altera Corporation August 2005 Causes ● Invalid 8B/10B code detected ● Running disparity error ● CRC error (if CRC implemented) Packet marked bad by ● ...
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... Instead, most of the signals are metastability-hardened, and incur a two- three-cycle latency. 3–56 SerialLite MegaCore Function User Guide CLK MRESET_N Atlantic Interface Transmit SerialLite MegaCore Function Variation Atlantic Interface Receive Transceiver Status Control MegaCore Function Version 1.1.0 Figure 3–32. The information High-Speed Serial Interface Altera Corporation August 2005 ...
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... Output STATUS_PORT[3] Output STATUS_PORT[4] Output STATUS_PORT[15..5] Output Altera Corporation August 2005 Table Description Link up. Indicates that the local side of the link has been successfully initialized and is running generated in the recovered clock domain internally, but is displayed in the system clock domain. Because the signal crosses domains and is metastability-hardened, there is a two- to three-cycle latency for the signal to be asserted and deasserted ...
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... Adjusts the termination on the transmitter differential pair Adjusts the output differential voltage Adjusts the amount of pre-emphasis given to the transmitted signal Adjusts the amount of equalization applied to the received signal Adjusts how lost signals are handled MegaCore Function Version 1.1.0 Description Altera Corporation August 2005 ...
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... SerialLite MegaCore function wizard allows you to make this selection. Table 3–45. Transmitter Termination Options 100 Ω (default) 120 Ω 150 Ω Output Differential Voltage (V Stratix GX transceivers allow you to customize the output differential voltage (V requirements. V Altera Corporation August 2005 Tables 3–43 Table ) handle different length, backplane, and receiver OD is illustrated in ...
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... A single static selected value is used for the V for all lanes. This is the default O D setting. TX_VODCTRL The bus is created, with three bits per lane. The V value determined by the value placed on these signals, according to Table 3–45. value are OD Altera Corporation August 2005 ...
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... This maximizes the data eye opening at the far- end receiver. Pre-emphasis is particularly useful in lossy transmission media. Altera Corporation August 2005 setting while the device is operating. You can set the OD value by asserting encoded values on the TX_VODCTRL bus, which is of each lane to be configured independently ...
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... This is the default setting. RX_EQUALIZATIONCTRL three bits per lane. The equalization value is determined by the value placed on these signals, according to Table MegaCore Function Version 1.1.0 Description bus is created, with 3–50. Description bus is created, with 3–51. Altera Corporation August 2005 ...
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... Table 3–51. Equalization Encoded Values Avoid pre-emphasis settings that, together with the V value greater than 1600 mV. Settings beyond this value do not damage the buffer, but prevent the operation of the device from being represented accurately. Altera Corporation August 2005 Pre-emphasis setting 0 (default) 1 ...
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... Option Signals with a differential voltage of less than 530 mV is considered lost, and a link error occurs. The internal flag defaults to indicate that a signal is always present. This is the default setting. MegaCore Function Version 1.1.0 Description Altera Corporation August 2005 ...
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... In the latter case, the settings for lane four would be read from the tables as if bits [11..9] were bits [2..0], so that a pre-emphasis setting of 1 for lane 4 would be achieved by placing 001 on bits [11..9]. Altera Corporation August 2005 , pre-emphasis, and equalization settings of each lane ...
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... MegaCore Function Version 1.1.0 Table 3–54. These signals can Description is selected. Three bits are O D 3–47. Table 3–50. Table 3–51. RX_SLPBK signal is high, all blocks TX_OUT[] signal. TX_OUT[] RX_IN[] signal, Altera Corporation August 2005 ...
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... Table 3–55. Optimization Settings Optimize for speed Optimize for size Altera Corporation August 2005 Option Various subtle aspects of the design use more flip-flops to provide higher speed. This is the default for designs with four or more lanes ...
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... Retry on error: the buffering and acknowledgment mechanisms can impact speed. Receive FIFO buffer size: large FIFO buffers increase fanout and may require longer routing to extend further inside the device. ® II Design Space Explorer is also a useful tool for MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... Altera Corporation August 2005 Lane count: running fewer lanes at higher bit rates, if possible, uses less logic (but places more of a burden on meeting performance). CRC: significant savings can be made by eliminating CRC particular, moving from CRC-32 to CRC-16 in high-lane-count designs ...
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... Pause duration: when you wish to optimize against starvation, you can reduce the size of the receive FIFOs needed by shortening the pause duration. Retry-on-error: this feature requires eight packet buffers, as compared to two packet buffers if the feature is not used. MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... The other end of the link restarts once it sees eight successive training sequences. 1 Altera Corporation August 2005 While the initial training sequences are being received, they may be processed through the SerialLite logic and presented at the Atlantic interface ...
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... SerialLite Link Configuration 3–72 SerialLite MegaCore Function User Guide MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... Verilog HDL IP functional simulation models. Description f For more information on IP functional simulation models, see the Simulating Altera in Third-Party Simulation Tools chapter in Volume 3 of the Quartus II Handbook. Altera provides models you can use for functional verification of the SerialLite MegaCore demonstration testbench, including scripts to run it, is also provided. This demonstration testbench, used with the ModelSim tool, demonstrates how to instantiate a model in a design ...
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... Optionally modify the list of simulation parameters in the <variation name>_tb_params.txt file to reflect the simulations you wish to perform. Execute the run do <variation name>_tb.do file using ModelSim. MegaCore Function Version 1.1.0 SerialLite High-Speed Core Serial Interface phasex0 xcvr Loopback phasex15 Status Monitor15 Altera Corporation August 2005 ...
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... If you inadvertently change the value to the left of the equal sign, restore it to its original name exactly, including case. Altera Corporation August 2005 The testbench waits for the main reset sequence to end. The testbench waits for the SerialLite link to come up. ...
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... Only applicable if the priority data port is enabled. The number of regular data packets. Controls the number of packets sent by the Atlantic generator to the regular data port. Only applicable if the regular data port is enabled and packet mode is selected Altera Corporation August 2005 ...
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... Not all parameters are available for any given link. For example, if you only instantiate the priority data port, editing the parameter list for the regular data port has no effect on the simulation. w Altera Corporation August 2005 Maximum Default 1 ...
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... Only applicable if the priority data port is enabled. The number of regular data packets. Controls the number of packets sent by the Atlantic generator to the regular data port. Only applicable if the regular data port is enabled and packet mode is selected Altera Corporation August 2005 ...
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... SerialLite Testbench Table 4–2. SerialLite IP Testbench Parameters (Other Simulator) (Part Parameter NUM_STREAM_TRANSACTIONS PRIORITY_PACKET_LENGTH DATA_PACKETS_LENGTH Altera Corporation August 2005 Minimum Maximum Default 1 (2^32)- byte 65,535 bytes 10 bytes 1 byte 65,535 bytes 256 bytes MegaCore Function Version 1.1.0 SerialLite MegaCore Function User Guide Description The number of streaming transactions ...
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... You can optionally set it to 1'b1 to set the error flag for that packet. Reserved for future use. taddress The field sets the address for the current packet for use in channel-muxing mode. Set this to 0 when channel muxing is disabled. Altera Corporation August 2005 ...
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... MegaCore. The task also supports the streaming mode if the data port is configured as such. By default, the monitor is configured for packet mode. To put the monitor into streaming mode, use a Verilog defparam on the packet_mode parameter, and set this to 0. Example Altera Corporation August 2005 Valid Values 1 - 65535 (bytes) 1'b0 or 1'b1 seriallite_tb.atl_gen_dat_inst.send_pkt (1'b1, 1'b1, 1'b0, 0, 8'h0, 16'd256, 1'b0) ...
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... This task is described in detail in “User Packet Data” on page seriallite_tb.atl_mon_dat_inst.rcv_pkt (1'b0, 0, 8'h0, 16'd256, 1'b0); MegaCore Function Version 1.1.0 Description field determines if the Atlantic signal is expected to be asserted at the field sets the expected field sets the expected size field determines 4–11. Altera Corporation August 2005 ...
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... To invoke the user_packet task, use the following syntax within the testbench: Table 4–5. User Packet Task Field Descriptions Field Location Altera Corporation August 2005 The send_pkt and rcv_pkt tasks are normally invoked using a Verilog fork and join statement. Each task must finish before invoking another similar task call ...
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... By default, the expected value inside each status monitor is 1'b0. 4–12 SerialLite MegaCore Function User Guide seriallite_tb.atl_gen_dat_inst.user_packet(8'hFE,1 6'h0); // SOP seriallite_tb.atl_gen_dat_inst.user_packet(8'hED,1 6'h1); seriallite_tb.atl_gen_dat_inst.user_packet(8'hCA,1 6'h2); seriallite_tb.atl_gen_dat_inst.user_packet(8'hBB,1 6'h3); seriallite_tb.atl_gen_dat_inst.user_packet(8'h1E,1 6'h4); // EOP. seriallite_tb.atl_gen_dat_inst.send_pkt(1'b1, 1'b1, 1'b0, 0, 8'h0, 16'd5, 1'b1); sp_en[4..0] = 5'b11111; seriallite_tb.stat_mon_inst0.set_expect(1); MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...
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... A simulation script allows you to run a simulation based on the simulation configuration you have chosen. To run the simulation while in the ModelSim Tcl environment, first ensure that the working directory is the one you specified in step page 1. Altera Corporation August 2005 4 of “Create a New Quartus II Project” on 2–5. ...
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... SerialLite MegaCore Function User Guide Run the simulation the Model Technology ModelSim-Altera simulation tool, run the simulation by typing the following command: do <variation name>_tb_ae. other versions of the ModelSim simulation tool, run the simulation by typing the following command: do < ...
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... However, the test was successful because the errors were detected. For this reason, simulation failure is not by itself an indication of a problem. Altera Corporation August 2005 Were all expected stimulus generated? Did all expected packets arrive and was the data error-free? ...
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... Configuring the Simulation 4–16 SerialLite MegaCore Function User Guide MegaCore Function Version 1.1.0 Altera Corporation August 2005 ...