IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 117

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

SerialLite Testbench
Altera Corporation
August 2005
Special Simulation Configuration Settings
The SerialLite MegaCore contains two settings that have a reduced value
in simulation.
The internal counter that controls the duration of the digital resets to the
ALTGXB megafunction counts up to 20 in simulation. This overrides the
default value of 1,000,000.
The clock compensation value determines when the clock compensation
sequence is inserted into the high-speed serial stream (when clock
compensation is enabled). In simulation, to minimize the time it takes for
the sequence to occur, the value is always 100 cycles, independent of the
actual clock compensation time value (100 or 300 ppm).
Waveform Generation
The simulation allows VCD file generation if WAVEFORM is tick defined.
All signals are included in the dump file.
Example
Add `define WAVEFORM to the testbench or +define+WAVEFORM to
the simulator command line to create a VCD dump file.
Testbench Timeout
The testbench uses a maximum simulation time to guard against infinite
loops or stuck simulations. The default value of 15000000 system clock
cycles is probably sufficient for most simulation runs. If more time is
needed for a particularly long run, you can increase the WATCHTIME
value.
For example, inside the testbench, add
`define WATCHTIME 55000000
Running a Simulation
A simulation script allows you to run a simulation based on the
simulation configuration you have chosen. To run the simulation while in
the ModelSim Tcl environment, first ensure that the working directory is
the one you specified in step
page
1.
Run ModelSim (vsim) to bring up the user interface.
2–5.
MegaCore Function Version 1.1.0
4
of
SerialLite MegaCore Function User Guide
“Create a New Quartus II Project” on
4–13