AT94K05AL-25DQU Atmel, AT94K05AL-25DQU Datasheet - Page 112

• Manufacturer Part Number: AT94K05AL-25DQU
• Manufacturer: Atmel

Specifications of AT94K05AL-25DQU

• Device System Gates: 5000
• Propagation Delay Time: 12.1ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Industrial
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Compliant

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Multiplier
AT94KAL Series FPSLIC
The multiplier is capable of multiplying two 8-bit numbers, giving a 16-bit result using only two
clock cycles. The multiplier can handle both signed and unsigned integer and fractional numbers
without speed or code size penalty. Below are some examples of using the multiplier for 8-bit
arithmetic.
To be able to use the multiplier, six new instructions are added to the AVR instruction set. These
are:
The MULSU and FMULSU instructions are included to improve the speed and code density for
multiplication of 16-bit operands. The second section will show examples of how to efficiently
use the multiplier for 16-bit arithmetic.
The component that makes a dedicated digital signal processor (DSP) specially suitable for sig-
nal processing is the multiply-accumulate (MAC) unit. This unit is functionally equivalent to a
multiplier directly connected to an arithmetic logic unit (ALU). The FPSLIC-based AVR Core is
designed to give FPSLIC the ability to effectively perform the same multiply-accumulate
operation.
The multiply-accumulate operation (sometimes referred to as multiply-add operation) has one
critical drawback. When adding multiple values to one result variable, even when adding positive
and negative values to some extent, cancel each other; the risk of the result variable to overrun
its limits becomes evident, i.e. if adding 1 to a signed byte variable that contains the value +127,
the result will be -128 instead of +128. One solution often used to solve this problem is to intro-
duce fractional numbers, i.e. numbers that are less than 1 and greater than or equal to -1. Some
issues regarding the use of fractional numbers are discussed.
A list of all implementations with key performance specifications is given in
• MUL, multiplication of unsigned integers
• MULS, multiplication of signed integers
• MULSU, multiplication of a signed integer with an unsigned integer
• FMUL, multiplication of unsigned fractional numbers
• FMULS, multiplication of signed fractional numbers
• FMULSU, multiplication of a signed fractional number and with an unsigned fractional
number
Table
4-24.
1138I–FPSLI–1/08