AT94K05AL-25DQU Atmel, AT94K05AL-25DQU Datasheet - Page 129
AT94K05AL-25DQU
Manufacturer Part Number
AT94K05AL-25DQU
Description
Manufacturer
Atmel
Datasheet
1.AT94K05AL-25DQU.pdf
(204 pages)
Specifications of AT94K05AL-25DQU
Device System Gates
5000
Propagation Delay Time
12.1ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Industrial
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Compliant
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4.29
4.29.1
1138I–FPSLI–1/08
UARTs
Data Transmission
The FPSLIC features two full duplex (separate receive and transmit registers) Universal Asyn-
chronous Receiver and Transmitter (UART). The main features are:
A block schematic of the UART transmitter is shown in
and the functionality is described in general for the two UARTs.
Figure 4-41. UART Transmitter
Note:
• Baud-rate Generator Generates any Baud-rate
• High Baud-rates at Low XTAL Frequencies
• 8 or 9 Bits Data
• Noise Filtering
• Overrun Detection
• Framing Error Detection
• False Start Bit Detection
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed UART Mode
1. n = 0, 1
XTAL
CONTROL LOGIC
GENERATOR
BAUD RATE
STORE UDRn
SHIFT ENABLE
BAUD x 16
IDLE
(1)
UART CONTROL AND
STATUS REGISTER
/16
DATA BUS
BAUD
(UCSRnB)
DATA BUS
AT94KAL Series FPSLIC
REGISTER (UDRn)
SHIFT REGISTER
UART I/O DATA
10(11)-BIT TX
Figure
UART CONTROL AND
TXCn
STATUS REGISTER
IRQ
(UCSRnA)
4-41. The two UARTs are identical
UDREn
IRQ
TXDn
PIN CONTROL
LOGIC
PE0/
PE2
129
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