PCA9600DP-T NXP Semiconductors, PCA9600DP-T Datasheet
PCA9600DP-T
Specifications of PCA9600DP-T
Related parts for PCA9600DP-T
PCA9600DP-T Summary of contents
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PCA9600 Dual bidirectional bus buffer Rev. 04 — 11 November 2009 1. General description The PCA9600 is designed to isolate I in point-to-point or multipoint applications 4000 pF. The PCA9600 is a higher-speed version of the P82B96. ...
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... Long distance point-to-point or multipoint architectures 4. Ordering information Table 1. Type number PCA9600D PCA9600DP 4.1 Ordering options Table 2. Type number PCA9600D PCA9600DP 5. Block diagram Fig 1. PCA9600_4 Product data sheet 2 C-buses operating at different logic levels (for example and 2 C-bus and SMBus (350 A) standard or Fm+ standard 2 ...
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... Figure 1 “Block diagram of PCA9600”. 2 C-bus pins SX (and SY) and transmit this state to pin TX Rev. 04 — 11 November 2009 PCA9600 Dual bidirectional bus buffer PCA9600DP GND 4 5 002aac837 Fig 3. Pin configuration for TSSOP8 (MSOP8) 2 C-bus 2 C-bus interface. These paths: ...
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... NXP Semiconductors The logic threshold voltage levels this I voltage V When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal 3 mA with C-bus specification for all I SMBus or other systems that use TTL switching levels guaranteed to sink an external addition to its internally sourced pull-up of typically 300 A (maximum ...
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... NXP Semiconductors Remark: Two or more I/Os must not be interconnected. The PCA9600 design does not support this configuration. Bidirectional I direction control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A ‘regular I PCA9600 will be propagated to SX/ ‘buffered LOW’ with a slightly higher voltage level. If this special ‘ ...
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... NXP Semiconductors When the device driving the PCA9600 improvement on the P82B96 as shown in however, and if the device driving the bus buffer is not I to use the micro already in the system and bit-bang using two GPIO pins) then here are some considerations that would point to using the P82B96 instead: • ...
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... NXP Semiconductors 9. Characteristics Table 6. Characteristics +85 C unless otherwise specified; voltages are specified with respect to GND with V amb unless otherwise specified. Typical values are measured at V Symbol Parameter Power supply V supply voltage CC I supply current CC I additional supply current ...
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... NXP Semiconductors Table 6. Characteristics …continued +85 C unless otherwise specified; voltages are specified with respect to GND with V amb unless otherwise specified. Typical values are measured at V Symbol Parameter Output logic LOW level Pins SX and SY V LOW-level output voltage voltage variation with temperature ...
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... NXP Semiconductors Table 6. Characteristics …continued +85 C unless otherwise specified; voltages are specified with respect to GND with V amb unless otherwise specified. Typical values are measured at V Symbol Parameter [5] Buffer response time pin TX pull-up resistor = 160 ; pin SX pull-up resistor = 2 capacitive load ...
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... NXP Semiconductors Fig 4. 800 V OL (mV) 700 (1) (2) 600 500 400 typical and limits over temperature. OL (1) Maximum. (2) Typical. Fig function of junction temperature 0.3 mA) OL 600 V IL (mV) 500 400 300 200 changes over temperature range. IL Fig function of junction temperature; IL maximum values PCA9600_4 ...
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... NXP Semiconductors 1400 V CC(max) (mV) 1200 1000 800 600 400 Fig 9. V bus release limit over temperature; CC maximum values PCA9600_4 Product data sheet 002aac075 1000 800 600 400 200 0 75 100 125 (1) Maximum. (2) Typical. Fig 10. Current sourced out of SX/ function of Rev. 04 — 11 November 2009 ...
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... NXP Semiconductors 10. Application information Refer to PCA9600 data sheet and application notes AN10658 and AN255 for more detailed application information. Fig 11. Interfacing a standard Fig 12. Galvanic isolation of I SDA SCL Fig 13. Long distance I PCA9600_4 Product data sheet C-bus SDA PCA9600 2 C-bus or one with TTL levels (e.g. SMBus) to higher voltage or higher current sink (e ...
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... NXP Semiconductors V CC1 R2 R2 SCL C-BUS MASTER SDA SY PCA9600 C2 C2 GND Fig 14. Driving ribbon or flat telephone cables Table 7. Examples of bus capability Refer to Figure 14 CC1 CC2 (V) cable ( ( 750 2 750 2.2 3.3 5 3.3 330 1 3.3 5 3.3 330 1 For more examples of faster alternatives for driving over longer cables such as Cat5 communication cable, see AN10658 . Communication at 1 MHz is possible over short cables and > ...
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... NXP Semiconductors 10.1 Calculating system delays and bus clock frequency local master bus V CCM SCL MASTER 2 I C-BUS GND (0 V) Effective delay of SCL at slave: 120 + 17V Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times V CCM MASTER 2 I C-BUS Effective delay of SCL at master: 115 + ( ...
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... NXP Semiconductors local master bus V CCM SDA MASTER 2 I C-BUS GND (0 V) Effective delay of SDA at master: 115 + 0.2( Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times Figure 15, with relatively large capacitances linking two I expressions for making the relevant timing calculations for 3 operation. ...
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... NXP Semiconductors the master reaching the slave rising edge reaching the master The master microcontroller should be programmed to produce a nominal SCL LOW period as follows: SCL LOW The actual LOW period will become (the programmed value + the stretching time B). When this actual LOW period is then less than the specified minimum, the specified minimum should be used ...
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... NXP Semiconductors The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+ 500 ns requirement. This system requires the bus LOW period, and therefore cycle time increased the system must run slightly below the 1 MHz limit. The possible maximum speed has a cycle period of 1033 ns or 968 kHz. ...
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... NXP Semiconductors ( 100 200 300 400 500 600 700 800 (1) TX output. (2) SX input. Fig 19. Propagation with V (SX pull- pull-up to 5.7 V) (1) RX input. (2) SX output. Fig 21. Propagation (SX pull- 10.2 Negative undershoot below absolute minimum value The reason why the IC pin reverse voltage on pins TX and specifi ...
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... NXP Semiconductors testing but it was not damaged. Whenever there is current flowing in any of these diodes it is possible that there can be faulty operation of any IC. For that reason we put a specification on the negative voltage that is allowed to be applied selected so that, at the highest allowed junction temperature, there will be a big safety factor that guarantees the diode will not conduct and then we do not need to make any 100 % production tests to guarantee the published specifi ...
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... NXP Semiconductors 10.2.1 Example with questions and answers Question falling edge measure undershoot at 800 mV at the linked TX, RX pins of the PCA9600 that is generating the LOW, but the PCA9600 data sheet specifies minimum 0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For PCA9600 the 0 ...
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... NXP Semiconductors Question: We have 2 meters of cable in a bus that joins the TX/RX sides of two PCA9600 devices. When one TX drives LOW the other PCA9600 TX/RX is driven to 0.8 V for over 50 ns. What is the expected value and the theoretically allowed value of undershoot? Answer: Because the cable joining the two PCA9600s is a ‘transmission line’ that will ...
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... NXP Semiconductors Question add 100 smaller. Is this a good idea? Answer: No not necessary to add any resistance. When the logic signal generated PCA9600 drives long traces or wiring with ICs other than PCA9600 being driven, then adding a Schottky diode (BAT54A) as shown in the wiring undershoot to a value that will not cause conduction of the IC’s internal diodes ...
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... NXP Semiconductors 11. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 10. Acronym CDM ESD HBM 2 I C-bus I PMBus SMBus TTL PCA9600_4 Product data sheet ...
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... NXP Semiconductors 14. Revision history Table 11. Revision history Document ID Release date PCA9600_4 20091111 • Modifications: Table 5 “Limiting • Added Section 10.2 “Negative undershoot below absolute minimum PCA9600_3 20090903 PCA9600_2 20080813 PCA9600_1 20080602 PCA9600_4 Product data sheet Data sheet status Change notice ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Application information 10.1 Calculating system delays and bus clock frequency ...