ACS8525AT Semtech, ACS8525AT Datasheet - Page 16

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Output DFS block (offering 77.76 MHz, 12E1, 16E1,
24DS1 or 16DS1). The frequency from APLL1 is four
times its input frequency i.e. 311.04 MHz when used with
a 77.76 MHz input. APLL1 is subsequently divided by 1, 2,
4, 6, 8, 12, 16 and 48 and these are available at the O1
and O2 Outputs.
DPLL2 & APLLs
DPLL2 is simpler than DPLL1. DPLL2 offers no PBO or
phase offset. The DPLL2 input can only be used to lock to
DPLL1. Unlike DPLL1, the DPLL2 Forward DFS block does
not always generate 77.76 MHz. The possible frequencies
are listed in Table 10, “APLL2 Frequencies,” on page 27.
Similar to DPLL1, the output of the DPLL2 Forward DFS
block is generated using DFS clocked by the 204.8 MHz
system clock and will have an inherent jitter of 4.9 ns.
The DPLL2 feedback DFS also has the facility to be able
to use the post APLL2 (jitter-filtered) clock to generate the
feedback locking frequency. Again, this will give the
maximum performance by using a low jitter feedback.
APLL2 block is also for multiplying and filtering. The input
to APLL2 can come either from the DPLL2 Forward DFS
block or from DPLL1. The input to APLL2 can be
programmed to be one of the following:
(a) Output from the DPLL2 Forward DFS block (12E1,
(b) 12E1 from DPLL1,
(c) 16E1 from DPLL1,
(d) 24DS1 from DPLL1,
(e) 16DS1 from DPLL1.
The frequency generated from the APLL2 is four times its
input frequency i.e. 311.04 MHz when used with a
77.76 MHz input. APLL2 is subsequently divided by 2, 4,
8, 12, 16, 48 and 64 and these are available at the O1
and 02 Outputs.
“Digital” Frequencies
The DPLL1 LF Output DFS block shown in the diagram,
clocked either by the DPLL1 77M Output DFS block or via
the APLL1, generates the single frequencies Digital1 and
Digital2 (see Table 11 and Table 12). The input clock
frequency of the DFS is always 77.76 MHz and as such
has a period of approximately 12 ns. The jitter generated
on the Digital outputs is relatively high, because they do
not pass through an APLL for jitter filtering. The minimum
level of jitter is when DPLL1 is in analog feedback mode,
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
24DS1, 16E1, 16DS1, E3, DS3, OC-N),
FINAL
Page 16
when the p-p jitter will be approximately 13 ns (equivalent
to a period of the DFS clock). The maximum jitter is
generated when in digital feedback mode, when the total
is approximately 18 ns.
The E1/DS1 Synthesis block generates the E1/DS1 rates
for the APLLs, using the output from DPLL1. It can
generate 12E1, 16E1, 16DS1 or 24DS1, for selection by
the multiplexers.
FrSync, MFrSync, 2 kHz and 8 kHz Clock Outputs
Whilst the FrSync and MFrSync Outputs are always
supplied from DPLL1, the 2 kHz and 8 kHz options
available from the O1 and O2 Outputs can be supplied
from either DPLL1 or DPLL2 (Reg. 7A Bit 7).
Multiplexers
Multiplexers MUX1 and MUX2 are used to select the
appropriate inputs to the Analog PLLs. The function they
represent is controlled by Reg. 65
cnfg_DPLL1_frequency.
APLL2 Input Selection using MUX 2
APLL1 Input Selection using MUX 1
Notes: (i) DPLL2 output cannot be selected for input to APLL1
DPLL2 selected for input to APLL2 (Reg. 65 Bit 6 = 0)
The input frequency is selected from the operating
frequency of DPLL2 (Reg. 64 Bits [2:0])
DPLL1 + LF Output DFS selected for Input to APLL2
DPLL1 (77.76 MHz) output fed to input of APLL1.
Analog feedback used in DPLL1 (Reg. 65 Bits [2:0] set
to 000)
DPLL1 (77.76 MHz) output fed to input of APLL1.
Digital feedback used in DPLL1 (Reg. 65 Bits [2:0] set
to 001)
DPLL1 + LF Output DFS selected for input to APLL1
• 12E1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 00)
• 16E1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 01)
• 24DS1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 10)
• 16DS1 (Reg. 65 Bit 6 = 1 and Bits [5:4] set to 11)
• 12E1 (Reg. 65 Bits [2:0] set to 010)
• 16E1 (Reg. 65 Bits [2:0] set to 011)
• 24DS1 (Reg. 65 Bits [2:0] set to 100)
• 16DS1 (Reg. 65 Bits [2:0] set to 101)
(ii) If both multiplexers select LF Output DFS, the same
frequency value must be selected in Reg. 65 Bits
[2:0] and Reg. 65 Bits [5:4].
ACS8525A LC/P
DATASHEET
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