ACS8525AT Semtech, ACS8525AT Datasheet - Page 95

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Address (hex):
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
Indep_FrSync/
MFrSync
Bit No.
Bit 7
[5:4]
[3:2]
[1:0]
6
7B (cont...)
cnfg_sync_phase
Sync_OC-N_
rates
Description
Sync_OC-N_rates
This allows the selected Sync input to synchronize
the OC-3 derived clocks in order to maintain
alignment between the FrSync output and output
clocks and allow a finer sampling precision of the
selected Sync input of either 19.44MHz or
38.88MHz.
Sync_phase_SYNC3
Register to control the sampling of the external Sync
input. Nominally the falling edge of the input is
aligned with the falling edge of the reference clock.
The margin is ±0.5 U.I. (Unit Interval).
Sync_phase_SYNC2
Register to control the sampling of the external Sync
input. Nominally the falling edge of the input is
aligned with the falling edge of the reference clock.
The margin is ±0.5 U.I. (Unit Interval).
Sync_phase_SYNC1
Register to control the sampling of the external Sync
input. Nominally the falling edge of the input is
aligned with the falling edge of the reference clock.
The margin is ±0.5 U.I. (Unit Interval).
Bit 6
Bit 5
Sync_phase_SYNC3
Description
Bit 4
FINAL
Page 95
(R/W) Register to configure the
behaviour of the synchronisation
for the external frame reference.
Bit Value
Bit 3
00
01
10
11
00
01
10
11
00
01
10
11
Sync_phase_SYNC2
0
1
Value Description
The OC-N rate clocks are not affected by the
selected Sync input. The selected Sync input is
sampled with a 6.48 MHz precision. 6.48MHz
should be provided as the input reference clock.
Allows the selected Sync input to operate with a
19.44 MHz or 38.88 MHz input clock reference.
Input sampling and output alignment to 19.44 MHz
is used when the current clock input is 19.44 MHz,
otherwise 38.88 MHz sampling precision is used.
On target.
0.5 U.I. early.
1 U.I. late.
0.5 U.I. late.
On target.
0.5 U.I. early.
1 U.I. late.
0.5 U.I. late.
On target.
0.5 U.I. early.
1 U.I. late.
0.5 U.I. late.
Bit 2
ACS8525A LC/P
Default Value
Bit 1
Sync_phase_SYNC1
DATASHEET
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0000 0000
Bit 0