ACS8525AT Semtech, ACS8525AT Datasheet - Page 82

• Manufacturer Part Number: ACS8525AT
• Manufacturer: Semtech

Specifications of ACS8525AT

• Lead Free Status / RoHS Status: Compliant

Address (hex):
Address (hex):
Revision 1.00/September 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[3:0]
Bit 7
[6:4]
7
3
69 (cont...)
6A
cnfg_DPLL1_acq_bw
Description
DPLL1_acquisition_bandwidth
Register to configure the bandwidth of DPLL1 when
acquiring phase lock on an input reference. Reg. 3B
Bit 7 is used to control whether this bandwidth is
not used or automatically switched to when not
phase locked.
cnfg_DPLL2_damping
Description
Not used.
DPLL2_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6C Bit 7,
cnfg_DPLL2_PD2_gain.
Not used.
Bit 6
Bit 6
DPLL2_PD2_gain_alog_8k
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 82
(R/W) Register to configure the
bandwidth of DPLL1, when not
phase locked to an input.
(R/W) Register to configure the
damping factor of DPLL2, along
with the gain of Phase Detector 2
in some modes.
Bit Value
Bit Value
Bit 3
Bit 3
11
00
01
10
-
-
-
Value Description
DPLL1, 18 Hz acquisition bandwidth.
DPLL1, 35 Hz acquisition bandwidth.
DPLL1, 70 Hz acquisition bandwidth.
Not used.
Value Description
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
-
Bit 2
Bit 2
ACS8525A LC/P
DPLL2_damping
Default Value
DPLL1_acquisition_bandwidth
Default Value
Bit 1
Bit 1
DATASHEET
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0001 0001
0001 0011
Bit 0
Bit 0