SC16C850IET-S NXP Semiconductors, SC16C850IET-S Datasheet - Page 37

SC16C850IET-S

Manufacturer Part Number
SC16C850IET-S
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C850IET-S

Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Number Of Channels
1
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SC16C850
Product data sheet
7.23 SC16C850 external reset condition and software reset
These two reset methods are identical and will reset the internal registers as indicated in
Table
Table 33.
Table 34.
Register
IER
FCR
ISR
LCR
MCR
LSR
MSR
EFCR
SPR
DLL
DLM
TXLVLCNT
RXLVLCNT
EFR
Xon1
Xon2
Xoff1
Xoff2
TXINTLVL
RXINTLVL
FLWCNTH
FLWCNTL
CLKPRES
RS485TIME
AFCR2
AFCR1
Output
TX
RTS
DTR
INT
IRQ
33.
Reset state for registers
Reset state for outputs
All information provided in this document is subject to legal disclaimers.
Reset state
IER[7:0] = 0
FCR[7:0] = 0
ISR[7:1] = 0; ISR[0] = 1
LCR[7:0] = 0
MCR[7:0] = 0
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR[7:4] = input signals; MSR[3:0] = 0
EFCR[7:0] = 0
SPR[7:0] = 1
undefined
undefined
TXLVLCNT[7:0] = 0
RXLVLCNT[7:0] = 0
EFR[7:0] = 0
undefined
undefined
undefined
undefined
TXINTLVL[7:0] = 0
RXINTLVL[7:0] = 0
FLWCNTH[7:0] = 0
FLWCNTL[7:0] = 0
CLKPRES[7:0] = 0
RS485TIME[7:0] = 0
AFCR2[7:0] = 0
AFCR1[7:0] = 0
Reset state
logic 1
logic 1
logic 1
logic 0
open-drain
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 2 — 11 November 2010
SC16C850
© NXP B.V. 2010. All rights reserved.
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