LC4128ZE-7TN100I Lattice, LC4128ZE-7TN100I Datasheet - Page 10

• Manufacturer Part Number: LC4128ZE-7TN100I
• Description: IC PLD 128MC 64I/O 7.5NS 100TQFP
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4128ZE-7TN100I

• Programmable Type: CPLD
• Number Of Macrocells: 128
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 7.5ns
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1026

Lattice Semiconductor
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the V
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down
resistor selectable on a “per-pin” basis. A fourth option is to provide none of these. The default in both hardware
and software is such that when the device is erased or if the user does not specify, the input structure is configured
to be a Pull-down Resistor.
Each ispMACH 4000ZE device I/O has an individually programmable output slew rate control bit. Each output can
be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew
setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer
reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated
lines, the fast slew rate can be used to achieve the highest speed.
The ispMACH 4000ZE family has an always on, 200mV typical hysteresis for each input operational at 3.3V and
2.5V. This provides improved noise immunity for slow transitioning signals.
Power Guard
Power Guard allows easier achievement of standby current in the system. As shown in Figure 9, this feature con-
sists of an enabling multiplexer between an I/O pin and input buffer, and its associated circuitry inside the device.
If the enable signal (E) is held low, all inputs (D) can be optionally isolated (guarded), such that, if any of these were
toggled, it would not cause any toggle on internal pins (Q), thus, a toggling I/O pin will not cause any internal
dynamic power consumption.
• LVTTL
• LVCMOS 3.3
• LVCMOS 2.5
CCO
supplied to its I/O bank. The I/O standards supported are:
From ORP
From ORP
To Macrocell
To GRP
GOE 0
GOE 1
GOE 2
GOE 3
• LVCMOS 1.8
• LVCMOS 1.5
• 3.3V PCI Compatible
Block Input Enable (BIE)
VCC
(From Block PT)
Power Guard
0
0
1
1
10
Power Guard Disable Fuse (PGDF)
I/O Bus Maintenance
ispMACH 4000ZE Family Data Sheet
VCCO
VCCO
CCO
supplied to its I/O bank. Outputs can