LC4128ZE-7TN100I Lattice, LC4128ZE-7TN100I Datasheet - Page 23

• Manufacturer Part Number: LC4128ZE-7TN100I
• Description: IC PLD 128MC 64I/O 7.5NS 100TQFP
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4128ZE-7TN100I

• Programmable Type: CPLD
• Number Of Macrocells: 128
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 7.5ns
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1026

Lattice Semiconductor
Timing Model
The task of determining the timing through the ispMACH 4000ZE family, like any CPLD, is relatively simple. The
timing model provided in Figure 16 shows the specific delay paths. Once the implementation of a given function is
determined either conceptually or from the software report file, the delay path of the function can easily be deter-
mined from the timing model. The Lattice design tools report the timing delays based on the same timing model for
a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The
external timing parameters are tested and guaranteed for every device. For more information on the timing model
and usage, refer to TN1168,
Figure 16. ispMACH 4000ZE Timing Model
SCLK
OE
Feedback
IN
From
t
t
Delays
t
t
PGRT
GCLK_IN
In/Out
PGRT
GOE
t
t
t
t
IOI
PGRT
IOI
IN
t
IOI
t
t
INREG
INDIO
ispMACH 4000ZE Timing Model Design and Usage
Control
t
Delays
ROUTE
t
t
BIE
BLA
t
PTCLK
t
t
t
PTSR
t
BCLK
MCELL
BSR
t
EXP
t
GPTOE
t
PTOE
23
Routing/GLB Delays
DATA
C.E.
S/R
t
MC Reg.
PDi
ispMACH 4000ZE Family Data Sheet
Note: Italicized items are optional delay adders.
Q
Register/Latch
Delays
Guidelines.
t
ORP
Oscillator/ Timer
Delays
t
t
t
Delays
OSCDIS
OSCOD
In/Out
OSCEN
t
t
t
t
t
FBK
BUF
IOO
DIS
EN
Out
Feedback
Feedback