SI5319B-C-GM Silicon Laboratories Inc, SI5319B-C-GM Datasheet - Page 48
![IC CLOCK MULT/ATTENUATOR 36QFN](/photos/16/12/161272/qfn-32_sml.jpg)
SI5319B-C-GM
Manufacturer Part Number
SI5319B-C-GM
Description
IC CLOCK MULT/ATTENUATOR 36QFN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5319C-C-GMR.pdf
(50 pages)
Specifications of SI5319B-C-GM
Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
36-VQFN
Frequency-max
*
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
QFN EP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Si5319
D
Revision 0.1 to Revision 0.2
Revision 0.2 to Revision 0.3
Revision 0.3 to Revision 0.4
Revision 0.4 to Revision 0.41
Revision 0.41 to Revision 0.42
Revision 0.42 to Revision 0.43
48
OCUMENT
Changed 1.8 V operating range to ±5%.
Updated Table 1 on page 4.
Updated Table 2 on page 5.
Added table under Figure 3 on page 14.
Updated "3. Functional Description" on page 16.
Clarified "5. Pin Descriptions: Si5319" on page 40.
Updated "5. Pin Descriptions: Si5319" on page 40.
Updated Table 1 on page 4.
Added "9. Si5319 Device Top Mark" on page 47.
Updated Table 1 on page 4.
Updated Figure 4, “Si5319 Typical Application
Circuit (I
Updated Figure 5, “Si5319 Typical Application
Circuit (SPI Control Mode),” on page 15.
Updated NC pin description in "5. Pin Descriptions:
Si5319" on page 40.
Updated "7. Package Outline: 36-Pin QFN" on page
44.
Added Figure 8, “Ground Pad Recommended
Layout,” on page 45.
Added register map documentation.
Updated Rise/Fall Time values.
Changed register address labels to decimal.
Updated the following:
Added specification for phase changes due to
temperature variation
Added information for the N32 register
Added
Corrected Pins 11 and 15 description in table.
Updated Thermal Resistance Junction to Ambient
typical specification.
ESD specifications
phase noise values
absolute Vdd maximum voltage
typical phase noise plot
JC
2
C Control Mode),” on page 15.
specification
C
HANGE
L
IST
Rev. 1.0
Revision 0.43 to Revision 1.0
Replaced the specification tables (tables 1 and 2
from rev. 0.43) with the specification tables from the
Si53x Reference Manual, rev 0.42.