PCKV857ADGG,518 NXP Semiconductors, PCKV857ADGG,518 Datasheet - Page 2

• Manufacturer Part Number: PCKV857ADGG,518
• Description: IC 1:10 2.5V PLL CLK-DRVR48TSSOP
• Manufacturer: NXP Semiconductors
• Type: PLL Clock Driverr

Specifications of PCKV857ADGG,518

• Input: SSTL-2
• Output: SSTL-2
• Frequency - Max: 250MHz
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935272504518; PCKV857ADGG-T; PCKV857ADGG-T

FEATURES
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DESCRIPTION
The PCKV857A is a high-performance, low-skew, low-jitter zero
delay buffer designed for 2.5 V V
differential data input and output levels.
The PCKV857A is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FB
inputs (CLK, CLK), the feedback clocks (FB
power input (AV
phase and frequency with CLK. When PWRDWN is LOW, all
outputs are disabled to HIGH impedance state (3-State), and the
PLL is shut down (LOW power mode). The device also enters the
LOW power mode when the input frequency falls below 20 MHz. An
input frequency detection circuit will detect the LOW frequency
condition and after applying a > 20 MHz input signal, the detection
circuit turns on the PLL again and enables the outputs.
When AV
purposes. The PCKV857A is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857A is characterized for operation from 0 to +70 °C.
ORDERING INFORMATION
Philips Semiconductors
2003 Jul 31
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
1-to-10 differential clock distribution
Very low skew (< 100 ps) and jitter (< 100 ps)
Operation from 2.2 V to 2.7 V AV
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16877 or
SSTV16857
Designed for DDR 266, 300, and 333 DIMM applications
Available in TSSOP-48 and TVSOP-48 packages
100-250 MHz differential 1:10 clock driver
48-Pin Plastic TSSOP (TVSOP)
OUT
, FB
48-Pin Plastic TSSOP
DD
OUT
PACKAGES
is grounded, the PLL is turned off and bypassed for test
) . The clock outputs are controlled by the clock
DD
). When PWRDWN is HIGH, the outputs switch in
DD
DD
and 2.5 V AV
and 2.3 V to 2.7 V V
TEMPERATURE RANGE
IN
, FB
DD
IN
0 to +70 °C
0 to +70 °C
), and the analog
operation and
DD
2
PIN CONFIGURATION
PCKV857ADGG
PCKV857ADGV
ORDER CODE
AGND
V
V
V
V
V
AV
GND
GND
GND
GND
GND
DDQ
DDQ
DDQ
CLK
CLK
DDQ
DDQ
Y
Y
Y
Y
Y
Y
DD
Y
Y
Y
Y
0
0
1
1
2
2
3
3
4
4
10
11
12
13
14
15
16
17
18
19
21
22
23
24
7
20
1
2
3
4
5
6
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
25
26
DRAWING NUMBER
GND
Y
Y
V
Y
Y
GND
GND
Y
Y
V
PWRDWN
FB
FB
V
FB
FB
GND
Y
Y
V
Y
Y
GND
5
5
DDQ
6
6
7
7
DDQ
DDQ
8
8
DDQ
9
9
SW00691
IN
IN
OUT
OUT
PCKV857A
SOT362-1
SOT480-1
Product data