ICS8536AG-01LF IDT, Integrated Device Technology Inc, ICS8536AG-01LF Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
ICS8536AG-01LF
Manufacturer Part Number
ICS8536AG-01LF
Description
IC CLK FAN BUFF MUX 1:6 24TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Series
HiPerClockS™r
Datasheet
1.ICS8536AG-01LF.pdf
(20 pages)
Specifications of ICS8536AG-01LF
Number Of Circuits
1
Ratio - Input:output
3:6
Differential - Input:output
Yes/Yes
Input
HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL, Crystal
Output
LVPECL
Frequency - Max
700MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
700MHz
Number Of Clock Inputs
3
Output Frequency
700MHz
Output Logic Level
LVPECL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1961-5
8536AG-01LF
ICS8536AG-01LF
8536AG-01LF
ICS8536AG-01LF
IDT
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
ICS8536-01
LOW SKEW, 1-TO-6, CRYSTAL/LVCMOS/DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
™
/ ICS
™
3.3V, 2.5V LVPECL FANOUT BUFFER
A
O
DDITIVE
FFSET
F
ROM
P
HASE
C
7
ARRIER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
J
F
ITTER
REQUENCY
(H
@ 155.52MHz (12kHz to 20MHz)
Z
)
ICS8536AG-01 REV. A FEBRUARY 24, 2009
Additive Phase Jitter
= 0.19ps typical