AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 37

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 17. AD9512 Register Map
Addr
(Hex)
00
01 to
33
34
35
36
37, 38,
39, 3A,
3B, 3C
3D
3E
3F
40
41
42, 43,
44
45
46, 47,
48, 49
4A
4B
4C
4D
4E
Parameter
Serial
Control Port
Configuration
FINE DELAY
ADJUST
Delay Bypass 4
Delay
Full-Scale 4
Delay Fine
Adjust 4
OUTPUTS
LVPECL OUT0
LVPECL OUT1
LVPECL OUT2
LVDS_CMOS
OUT 3
LVDS_CMOS
OUT 4
CLK1 AND
CLK2
Clocks Select,
Power-Down
(PD) Options
DIVIDERS
Divider 0
Divider 0
Divider 1
Divider 1
Divider 2
Bit 7 (MSB)
(Bidirectional
SDO Inactive
Bypass
Bypass
Mode)
Not Used
Not Used
Not Used
Not Used
Not Used
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Bit 6
Sync
Sync
First
LSB
Not Used
Not Used
Not Used
No
No
Bit 5
Reset
Force
Force
CLKs
Soft
PD
in
Ramp Capacitor <5:3>
Rev. A | Page 37 of 48
Not Used
Bit 4
Instruction
Driver On
Driver On
Not Used
Start H/L
Start H/L
Inverted
Inverted
CMOS
CMOS
Long
5-Bit Fine Delay <5:1>
Not Used
Not Used
Not Used
Not Used
Bit 3
Select
Select
Logic
Logic
Used
Output Level
Output Level
Output Level
Not
<3:2>
<3:2>
<3:2>
Phase Offset <3:0>
Phase Offset <3:0>
Bit 2
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
CLK2
Output Level
Output Level
PD
Ramp Current <2:0>
Not Used
<2:1>
<2:1>
Bit 1
CLK1
PD
Power-Down
Power-Down
Power-Down
<1:0>
<1:0>
<1:0>
Bit 0
(LSB)
Not Used
Output
Output
Bypass
Power
Power
CLK IN
Select
Def.
Value
(Hex)
10
01
00
00
08
08
08
02
02
01
00
00
11
00
33
Notes
Fine
Delays
Bypassed
Bypass
Delay
Max. Delay
Full-Scale
Min. Delay
Value
ON
ON
ON
LVDS, ON
LVDS, ON
Input
Receivers
All Clocks
ON, Select
CLK1
Divide by 2
Phase = 0
Divide by 4
Phase = 0
Divide by 8
AD9512