AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 39

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER MAP DESCRIPTION
Table 18 lists the AD9512 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle
brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 18 describes the
functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 17.
Table 18. AD9512 Register Descriptions
Reg.
Addr.
(Hex)
00
00
00
00
00
01 to 33 <7:0>
34
34
35
35
35
36
Bit(s)
<3:0>
<4>
<5>
<6>
<7>
<0>
<7:1>
<2:0>
<5:3>
<7:6>
<0>
Name
Serial Control Port
Configuration
Long Instruction
Soft Reset
LSB First
SDO Inactive
(Bidirectional
Mode)
Not Used
Fine Delay Adjust
Delay Control
OUT4
Ramp Current
OUT4
Ramp Capacitor
OUT4
Description
Any changes to this register takes effect immediately. Register 5Ah<0> Update Registers
does not have to be written.
Not Used.
When this bit is set (1), the instruction phase is 16 bits. When clear (0), the instruction phase
is 8 bits. The default, and only, mode for this part is long instruction (Default = 1b).
When this bit is set (1), the chip executes a soft reset, restoring default values to the internal
registers, except for this register, 00h. This bit is not self-clearing. A clear (0) has to be written
to it in order to clear it.
When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register
addressing increments. If this bit is clear (0), data is oriented as MSB first and register
addressing decrements. (Default = 0b, MSB first.)
When set (1), the SDO pin is tri-state and all read data goes to the SDIO pin. When clear (0),
the SDO is active (unidirectional mode). (Default = 0b).
Not Used.
Delay Block Control Bit.
Bypasses Delay Block and Powers It Down (Default = 1b).
Not Used.
The slowest ramp (200 μs) sets the longest full scale of approximately 10 ns.
<2>
0
0
0
0
1
1
1
1
Selects the Number of Capacitors in Ramp Generation Circuit.
More Capacitors => Slower Ramp.
<5>
0
0
0
0
1
1
1
1
Not Used.
Not Used.
Rev. A | Page 39 of 48
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
<1>
<4>
<0>
0
1
0
1
0
1
0
1
<3>
0
1
0
1
0
1
0
1
Ramp Current (μs)
200
400
600
800
1000
1200
1400
1600
Number of Capacitors
4 (Default)
3
3
2
3
2
2
1
AD9512