AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 5

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING CHARACTERISTICS
Table 3.
Parameter
LVPECL
PROPAGATION DELAY, t
OUTPUT SKEW, LVPECL OUTPUTS
LVDS
PROPAGATION DELAY, t
OUTPUT SKEW, LVDS OUTPUTS
CMOS
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS OUTPUTS
LVPECL-TO-LVDS OUT
LVPECL-TO-CMOS OUT
LVDS-TO-CMOS OUT
Output Rise Time, t
Output Fall Time, t
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUT1 to OUT0 on Same Part, t
OUT1 to OUT2 on Same Part, t
OUT0 to OUT2 on Same Part, t
All LVPECL OUT Across Multiple Parts, t
Same LVPECL OUT Across Multiple Parts, t
Output Rise Time, t
Output Fall Time, t
OUT3 to OUT4
OUT3 to OUT4 on Same Part, t
All LVDS OUTs Across Multiple Parts, t
Same LVDS OUT Across Multiple Parts, t
Output Rise Time, t
Output Fall Time, t
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUT3 to OUT4 on Same Part, t
All CMOS OUT Across Multiple Parts, t
Same CMOS OUT Across Multiple Parts, t
Output Skew, t
Output Skew, t
Output Skew, t
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
SKP_V
SKP_C
SKV_C
FP
FL
FC
RP
RL
RC
PECL
LVDS
CMOS
, CLK-TO-LVPECL OUT
, CLK-TO-LVDS OUT
, CLK-TO-CMOS OUT
SKP
SKP
SKP
SKV
SKC
2
2
2
2
2
SKV_AB
SKC_AB
SKP_AB
SKV_AB
SKC_AB
SKP_AB
3
3
3
1
3
3
1
1
3
Min
335
375
70
15
45
0.99
1.04
−85
1.02
1.07
−140
0.74
0.88
158
Rev. A | Page 5 of 48
Typ
130
130
490
545
0.5
100
45
65
200
210
1.33
1.38
0.9
681
646
1.39
1.44
1
+145
0.92
1.14
353
Max
180
180
635
695
140
80
90
275
130
350
350
1.59
1.64
+270
450
325
865
992
1.71
1.76
+300
650
500
1.14
1.43
506
ps
ns
ns
ns
Unit
ps
ps
ps
ps/°C
ps
ps
Ps
ps
ps
ps
ps
ns
ps/°C
ps
ps
ps
ps
ps
ps/°C
ps
ps
ns
ns
ps
Test Conditions/Comments
Termination = 50 Ω to V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 100 Ω differential
Output level 40h (41h) <2:1> = 01b
3.5 mA termination current
20% to 80%, measured differentially
80% to 20%, measured differentially
Delay off on OUT4
Delay off on OUT4
B outputs are inverted; termination = open
20% to 80%; C
80% to 20%; C
Delay off on OUT4
Delay off on OUT4
Everything the same; different logic type
LVPECL to LVDS on same part
Everything the same; different logic type
LVPECL to CMOS on same part
Everything the same; different logic type
LVDS to CMOS on same part
LOAD
LOAD
= 3 pF
= 3 pF
S
− 2 V
AD9512