ADF4360-2BCPZ Analog Devices Inc, ADF4360-2BCPZ Datasheet - Page 9

• Manufacturer Part Number: ADF4360-2BCPZ
• Description: IC SYNTHESIZER/VCO 24-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-2BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.17GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 2.15GHz
• Pll Type: Frequency Synthesis
• Frequency: 2.17GHz
• Supply Current: 10mA
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4360-2EBZ1 - BOARD EVALUATION FOR ADF4360-2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, or 32/33 and is based on a synchronous 4/5 core. There is
a minimum divide ratio possible for fully contiguous output
frequencies; this minimum is determined by P, the prescaler
value, and is given by (P
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feedback
counter. The counters are specified to work when the prescaler
output is 300 MHz or less. Thus, with a VCO frequency of
2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9
is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is
where:
f
P is the preset modulus of the dual-modulus prescaler (8/9,
16/17, and so on).
B is the preset divide ratio of the binary 13-bit counter (3 to 8,191).
A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).
f
VCO
REFIN
is the output frequency of the VCO.
f
is the external reference frequency oscillator.
VCO
= [(P × B) + A] × f
REF
IN
NC
POWER-DOWN
Figure 10. Reference Input Stage
SW1
CONTROL
NO
2
NC
− P).
SW3
SW2
REFIN
100kΩ
/R
BUFFER
TO R COUNTER
IN
pin
Rev. B | Page 9 of 24
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 12 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
R counter latch, ABP2 and ABP1, control the width of the pulse
(see Table 9).
CP OUTPUT
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
FROM VCO
HI
HI
Figure 12. PFD Simplified Schematic and Timing (In Lock)
D1
D2
CLR1
CLR2
U1
U2
N = BP + A
N DIVIDER
MODULUS
CONTROL
Q1
Q2
Figure 11. A and B Counters
PROGRAMMABLE
ABP1
PRESCALER
UP
DOWN
P/P+1
DELAY
ABP2
LOAD
LOAD
COUNTER
COUNTER
13-BIT B
5-BIT A
U3
ADF4360-2
CPGND
V
P
TO PFD
CHARGE
PUMP
CP