CY22150FZXC Cypress Semiconductor Corp, CY22150FZXC Datasheet
CY22150FZXC
Specifications of CY22150FZXC
CY22150FZXC
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CY22150FZXC Summary of contents
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... XIN OSC. XOUT Serial SDAT Programming SCLK Interface Cypress Semiconductor Corporation Document #: 38-07104 Rev. *I One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator ■ Nonvolatile reprogrammable technology allows easy customi- zation, quick turnaround on design changes and product perfor- mance enhancements, and better inventory control. Parts can ...
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Pin Configuration Table 1. Pin Definitions Name Number Description XIN 1 Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting ...
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Frequency Calculation and Register Definitions The CY22150 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, ...
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Default Startup Condition for the CY22150 The default (programmed) condition of the device is generally set by the distributor who programs the device using a customer specific JEDEC file produced by CyClocksRT™. Parts shipped from the factory are blank and ...
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Table 3. Programmable Crystal Input Oscillator Gain Settings Cap Register Settings Effective Load Capacitance (CapLoad) Crystal ESR Crystal Input MHz Frequency MHz MHz MHz Table 4. Bit Locations ...
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Stable operation of the CY22150 cannot be guaranteed if the value of (P *(REF above 400 MHz or below total total 100 MHz. Registers 40H, 41H, and 42H are defined in PLL Post Divider Options [OCH(7..0)], [47H(7..0)] The ...
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Table 11. Register 40H Change Pump Bit Settings Address D7 D6 40H 1 1 Although using the above table guarantees stability recom- mended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings ...
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Table 14. CLKOE Bit Setting Address D7 D6 09H 0 0 Programmable Interface Timing The CY22150 uses a two-wire serial-interface SDAT and SCLK that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is ...
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START Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data SDAT + START DA6 DA5DA0 R/W ACK + SCLK Parameter f Frequency of SCLK SCLK Start mode time from SDA LOW to SCL LOW CLK SCLK LOW period ...
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Applications Controlling Jitter Jitter is defined in many ways including: phase noise, long term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deter- ministic. These jitter terms are usually given in terms of rms, peak to peak, or ...
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Absolute Maximum Conditions Parameter V Supply Voltage DD V I/O Supply Voltage DDL T Storage Temperature S T Junction Temperature J Package Power Dissipation – Commercial Temp Package Power Dissipation – Industrial Temp Digital Inputs Digital Outputs Referred to V ...
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AC Electrical Characteristics [7] Parameter Name t1 Output Frequency, Commercial Temp Output Frequency, Industrial Temp t2 Output Duty Cycle LO t2 Output Duty Cycle HI t3 Rising Edge Slew LO Rate (V = 2.5V) DDL t4 Falling Edge Slew LO ...
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... CY22150KFI 16-Pin TSSOP [10] CY22150KZI-xxx 16-Pin TSSOP [10] CY22150KZI-xxxT 16-Pin TSSOP- Tape and Reel Pb-Free [11] CY22150FZXC 16-Pin TSSOP [11] CY22150FZXCT 16-Pin TSSOP - Tape and Reel [11] CY22150FZXI 16-Pin TSSOP [11] CY22150FZXIT 16-Pin TSSOP - Tape and Reel [10, 11] CY22150ZXC-xxx 16-Pin TSSOP [10, 11] CY22150ZXC-xxxT 16-Pin TSSOP- Tape and Reel ...
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Package Diagram Figure 11. 16-Pin TSSPO 4.40 mm Body Z16.173 1 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document #: 38-07104 Rev. *I PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT ...
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Document History Page Document Title: CY22150 One-PLL General-Purpose Flash-Programmable and 2-Wire Serially-Programmable Clock Gen- erator Document Number: 38-07104 ECN Issue Orig. of REV. NO. Date Change ** 107498 08/08/01 *A 110043 02/06/02 *B 113514 05/01/02 *C 121868 12/14/02 *D 125453 ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...