CY22150KFZXC Cypress Semiconductor Corp, CY22150KFZXC Datasheet - Page 8

• Manufacturer Part Number: CY22150KFZXC
• Description: IC CLOCK GEN PROG FLASH 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY22150KFZXC

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: Clock
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 133 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 0.08 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Number Of Elements: 1
• Supply Current: 45mA
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY30700 - KIT PROG FOR CY22150
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 14. CLKOE Bit Setting
Programmable Interface Timing
The CY22150 uses a two-wire serial-interface SDAT and SCLK
that operates up to 400 kbits/second in Read or Write mode. The
basic Write serial format is as follows.
Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); eight-bit Memory Address (MA); ACK;
eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK;
eight-bit data in MA+2; ACK; and so on until STOP bit.The basic
serial format is illustrated in
Data Valid
Data is valid when the Clock is HIGH, and may only be transi-
tioned when the clock is LOW, as illustrated in
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in
.
Document #: 38-07104 Rev. *I
Address
09H
SDAT Write
Multiple
Contiguous
Registers
SDAT Read
Multiple
Contiguous
Registers
Figure 5
Start Signal
Start Signal
D7
0
on page 9.
Figure 4
R/W = 0
R/W = 0
7-bit
Device
Address
7-bit
Device
Address
SDAT
SCLK
1-bit
1-bit
D6
0
on page 8.
ACK
ACK
Slave
1-bit
1-bit
Slave
Register
Address
(XXH)
Register
Address
(XXH)
8-bit
8-bit
Figure 3. Data Valid and Data Transition Periods
V
V
IH
IL
1-bit
Slave
ACK
1-bit
Slave
ACK
Figure
Figure 4. Data Frame Architecture
Register
Data
(XXH)
7-Bit
Device
Address (XXH)
8-bit
CLK6
D5
CLK
Data valid
3.
1-bit
Slave
ACK
1-bit
R/W = 1
HIGH
(XXH+1)
Register
Data
Register
Data
8-bit
8-bit
CLK5
1-bit
Slave
ACK
1-bit
Master
ACK
D4
Transition to next bit
CLK
Register
Data
(XXH+2)
Register
Data
(XXH+1)
t
8-bit
8-bit
DH
Start Sequence – Start frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a Start signal is given, the next
eight-bit data must be the device address (seven bits) and a R/W
bit, followed by register address (eight bits) and register data
(eight bits).
Stop Sequence – Stop frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During Write mode, the CY22150 responds with an ACK pulse
after every eight bits. This is accomplished by pulling the SDAT
line LOW during the N*9
on page 9. (N = the number of eight-bit segments transmitted.)
During Read mode, the ACK pulse after the data packet is sent
is generated by the master
LOW
t
SU
LCLK4
1-bit
Slave
ACK
1-bit
Master
ACK
D3
(FFH)
(FFH)
Register
Data
Register
Data
8-bit
8-bit
1-bit
Slave
ACK
1-bit
Master
ACK
Register
Data
(00H)
Register
Data
(00H)
LCLK3
8-bit
8-bit
th
D2
clock cycle, as illustrated in
1-bit
Slave
ACK
1-bit
Master
ACK
LCLK2
D1
1-bit
Slave
ACK
1-bit
Master
ACK
Stop Signal
Stop Signal
CY22150
Page 8 of 16
LCLK1
D0
Figure 6
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