LMK02000ISQ/NOPB National Semiconductor, LMK02000ISQ/NOPB Datasheet - Page 13

• Manufacturer Part Number: LMK02000ISQ/NOPB
• Description: IC CLOCK CONDITIONER PREC 48-LLP
• Manufacturer: National Semiconductor
• Type: Clock Conditionerr

Specifications of LMK02000ISQ/NOPB

• Pll: Yes
• Input: Clock
• Output: LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Frequency - Max: 800MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Frequency-max: 800MHz
• For Use With: LMK02000EVAL-1 - BOARD EVAL WITH 245.76 VCXOLMK02000EVAL2 - BOARD EVALUATION FOR LMK02000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMK02000ISQ; LMK02000ISQTR

2.3 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Reg-
ister R0 controls CLKout0, Register R1 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
Aside from this, the functions of these bits are identical. The
X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 7.
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
blocks in the signal path and therefore incurs a delay relative
to the bypass mode. The different MUX modes and associ-
ated delays are listed below.
RESET
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
DIV4
EN_CLKout_Global
POWERDOWN
PLL_CP_TRI
PLL_CP_POL
PLL_MUX
PLL_R
PLL_CP_GAIN
PLL_N
Bit Name
Bit Value
Default
760
10
0
0
0
1
0
0
1
0
0
0
0
0
No reset, normal operation
Bypassed
Disabled
Divide by 2
0 ps
PDF
Normal - CLKouts normal
Normal - Device active
Normal - PLL active
Negative Polarity CP
Disabled
R divider = 10
100 uA
N divider = 760
≤
20 MHz
Bit State
13
2.3.1 RESET Bit -- R0 only
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit. If this bit is set, all other R0
bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
CLKoutX_MUX
Reset to power on defaults
CLKoutX mux mode
CLKoutX enable
CLKoutX clock divide
CLKoutX clock delay
Phase Detector Frequency
Global clock output enable
Device power down
TRI-STATE PLL charge pump
Polarity of charge pump
Multiplexer control for LD pin
PLL R divide value
Charge pump current
PLL N divide value
[1:0]
0
1
2
3
Bit Description
Bypassed (default)
Divided and
Delayed
Delayed
Divided
Mode
Register
R0 to R7
R11
R14
R15
(In addition to the
(In addition to the
R0
Bypass Mode
Added Delay
programmed
programmed
Relative to
100 ps
400 ps
500 ps
delay)
delay)
0 ps
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Location
18:17
23:20
31:30
15:8
19:8
25:8
Bit
7:4
31
16
15
27
26
25
24