CY7B991V-5JI Cypress Semiconductor Corp, CY7B991V-5JI Datasheet - Page 16
![IC CLK BUFF SKEW 8OUT 32PLCC](/photos/16/11/161138/plcc32_sml.jpg)
CY7B991V-5JI
Manufacturer Part Number
CY7B991V-5JI
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Series
RoboClock+™r
Datasheet
1.CY7B991-7JXC.pdf
(20 pages)
Specifications of CY7B991V-5JI
Number Of Circuits
1
Package / Case
32-PLCC
Pll
Yes
Input
LVTTL
Output
LVTTL
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
80MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
3.63 V
Supply Voltage (min)
2.97 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7B991V-5JI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7B991V-5JI
Manufacturer:
CYP
Quantity:
20 000
Figure 10
of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire
delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumu-
lates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers
in series.
Document Number: 38-07138 Rev. *E
SYSTEM
CLOCK
shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 10. Board-to-Board Clock Distribution
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
L4
L1
L2
L3
Z
0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
Z
Z
0
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
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