CY7B991V-5JI Cypress Semiconductor Corp, CY7B991V-5JI Datasheet - Page 5
![IC CLK BUFF SKEW 8OUT 32PLCC](/photos/16/11/161138/plcc32_sml.jpg)
CY7B991V-5JI
Manufacturer Part Number
CY7B991V-5JI
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Series
RoboClock+™r
Datasheet
1.CY7B991-7JXC.pdf
(20 pages)
Specifications of CY7B991V-5JI
Number Of Circuits
1
Package / Case
32-PLCC
Pll
Yes
Input
LVTTL
Output
LVTTL
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
80MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
3.63 V
Supply Voltage (min)
2.97 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7B991V-5JI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7B991V-5JI
Manufacturer:
CYP
Quantity:
20 000
Figure 2
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in
Matrix”
inputs can have a removable jumper to ground, or be tied LOW
through a 100Ω resistor. This enables an external tester to
change the state of these pins.
Document Number: 38-07138 Rev. *E
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
(N/A)
(N/A)
(N/A)
(N/A)
1Fx
2Fx
MM
MH
HM
HH
LM
LH
ML
HL
LL
on page
shows the typical outputs with FB connected to a zero skew output.
4.
LL/HH
(N/A)
(N/A)
(N/A)
(N/A)
3Fx
4Fx
MM
MH
HM
HH
LM
LH
ML
HL
For testing purposes, any of the three level
REFInput
FBInput
DIVIDED
INVERT
– 6t
– 4t
– 3t
– 2t
– 1t
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output
+1t
+2t
+3t
+4t
+6t
0t
U
U
U
U
U
U
U
U
U
U
U
“Skew Select
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
[4]
CY7B991
CY7B992
Page 5 of 20
[+] Feedback