CY2213ZXC-2T Cypress Semiconductor Corp, CY2213ZXC-2T Datasheet - Page 7

• Manufacturer Part Number: CY2213ZXC-2T
• Description: IC PROG PECL CLOCK GEN 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2213ZXC-2T

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: LVPECL
• Ratio - Input:output: 1:2
• Differential - Input:output: No/Yes
• Frequency - Max: 400MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 500MHz
• Maximum Input Frequency: 133 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 125 MHz to 500 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07263 Rev. *E
The PECL differential driver is designed for low-voltage,
high-frequency operation. It significantly reduces the transient
switching noise and power dissipation when compared to
conventional CMOS drivers. The nominal value of the channel
impedance is 50 . The pull-up and pull-down resistors provide
matching channel termination. The combination of the differ-
ential driver and the output network determines the voltage
swing on the channel. The output clock is specified at the
measurement point indicated in Figure 5 and Figure 6.
Signal Waveforms
A physical signal that appears at the pins of the device is
deemed valid or invalid depending on its voltage and timing
relations with other signals. This section defines the voltage
and timing waveforms for the input and output pins of the
CY2213. The Device Characteristics tables list the specifica-
tions for the device parameters that are defined here.
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms.
Figure 10 shows the definition of period jitter with respect to
the falling edge of the CLK signal. Period jitter is the difference
between the minimum and maximum cycle times over many
cycles (typically 12800 cycles at 400 MHz). Equal require-
Table 1. Definition of Device Parameters
V
V
t
CR
Parameter
OH
IH
, V
, t
, V
CF
IL
OL
V(t)
CLK
CLKB
Clock output high and low voltages
V
Clock output rise and fall times
Definition
DD
Figure 8. Voltage Waveforms
LVCMOS input high and low voltages
Figure 9. Duty CycleJitter
t
DC = t
CF
t
CYCLE
PW+
/t
Input and Output voltage waveforms are defined as shown in
Figure 8. Rise and fall times are defined as the 20% and 80%
measurement points of V
The device parameters are defined in Table 1. Figure 9 shows
the definition of long-term duty cycle, which is simply the CLK
waveform high-time divided by the cycle time (defined at the
crossing point). Long-term duty cycle is the average over
many (> 10,000) cycles. DC is defined as the output clock
long-term duty cycle.
ments apply for rising edges of the CLK signal. t
as the output period jitter.
Figure 11 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle
jitter is the difference between cycle times of adjacent cycles
over many cycles (typically 12800 cycles at 400 MHz). Equal
requirements apply for rising edges of the CLK signal. t
defined as the clock output cycle-to-cycle jitter.
CYCLE
t
CR
t
PW+
OHmin
– V
OLmax
80%
20%
.
V
V
OHmin
OLmax
CY2213
Page 7 of 10
JP
is defined
JC
is
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