CY2XF23FLXCT Cypress Semiconductor Corp, CY2XF23FLXCT Datasheet - Page 8

• Manufacturer Part Number: CY2XF23FLXCT
• Description: IC XTAL OSC LVDS I2C 6CLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY2XF23FLXCT

• Pll: Yes
• Input: Crystal
• Output: LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/Yes
• Frequency - Max: 690MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 6-CLCC
• Frequency: *
• Count: *
• Operating Supply Voltage (typ): 2.5/3.3
• Output Level: LVDS
• Symmetry Max: 60%
• Operating Temp Range: 0C to 70C
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC Electrical Characteristics
AC Electrical Characteristics
Document Number: 001-53145 Rev. *D
ΔV
V
V
V
I
I
I
I
C
C
F
FSC
FSI
AG
T
T
T
T
T
Parameter
Notes
IH0
IH1
IL0
IL1
5. Not 100% tested, guaranteed by design and characterization.
6. This parameter is specified in CyClockWizard software.
7. Frequency stability is the maximum variation in frequency from F
8. Typical phase noise specs for factory programmed devices are listed in the
OLS
IH
IL
OUT
DC
R
LOCK
LSER
Jitter(φ)
IN0
IN1
Parameter
, T
OS
[5]
[5]
F
Change in V
complementary output states
Output low voltage (SDA)
Input high voltage
Input low voltage
Input high current (SDA)
Input high current (SCLK)
Input low current (SDA)
Input low current (SCLK)
Input capacitance (SDA)
Input capacitance (SCLK)
Output frequency
Frequency stability, commercial
devices
Frequency stability, industrial
devices
Aging, 10 years
Output duty cycle
Output rise and fall time
Startup time
Relock time
RMS phase jitter (random)
[7]
[7]
Description
OS
Description
between
[6]
[5]
(continued)
PRELIMINARY
V
between CLK and CLK#
I
Input = V
Input = V
Input = V
Input = V
OL
V
V
F > 450 MHz, measured at zero crossing
measured from the time
V
Time for CLK to reach valid frequency from
serial bus change to select bits in register
40h, measured from I
F
Pre-defined factory configurations
F <= 450 MHz, measured at zero crossing
20% and 80% of full output swing
Time for CLK to reach valid frequency
DD
OUT
DD
DD
DD
= 4 mA
0
= 3.3 V or 2.5 V, R
. It includes initial accuracy, plus variation from temperature and supply voltage.
= min to max, T
= min to max, T
= V
= 106.25 MHz (12 kHz to 20 MHz)
DD
DD
DD
SS
SS
(min.)
Standard and Application-Specific Factory Configurations
Condition
Condition
A
A
2
= 0°C to 70°C
= –40° to 85°C
TERM
C STOP
= 100 Ω
[8]
0.7*V
Min
–50
–20
–
–
–
–
–
–
–
DD
Min
50
45
40
–
–
–
–
–
–
–
See Note 8
Typ
15
–
–
–
–
–
–
–
–
4
0.35
Typ
50
50
–
–
–
–
–
–
1
table on page 2.
0.1*V
0.3*V
Max
115
50
10
–
–
–
–
–
Max
690
±35
±55
±15
CY2XF23
1.0
DD
DD
55
60
5
1
–
Page 8 of 14
Unit
mV
μA
μA
μA
μA
pF
pF
V
V
V
MHz
Unit
ppm
ppm
ppm
ms
ms
ns
ps
ps
%
%
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