PCF2123TS/1,112 NXP Semiconductors, PCF2123TS/1,112 Datasheet

IC SPI RTC/CALENDAR 14-TSSOP

PCF2123TS/1,112

Manufacturer Part Number
PCF2123TS/1,112
Description
IC SPI RTC/CALENDAR 14-TSSOP
Manufacturer
NXP Semiconductors
Type
Clock/Calendar/Alarmr
Datasheets

Specifications of PCF2123TS/1,112

Package / Case
14-TSSOP
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.1 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Function
Clock, Calendar
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.1 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935286384112
PCF2123TS/1
PCF2123TS/1
1. General description
2. Features and benefits
3. Applications
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in
The PCF2123 is a CMOS
applications. Data is transferred serially via a Serial Peripheral Interface (SPI-bus) with a
maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing
the possibility to generate a wake-up signal on an interrupt pin. An offset register allows
fine tuning of the clock.
PCF2123
SPI Real time clock/calendar
Rev. 4 — 22 December 2010
Real time clock provides year, month, day, weekday, hours, minutes, and seconds
based on a 32.768 kHz quartz crystal
Low backup current while running: typical 100 nA at V
Resolution: seconds to years
Watchdog functionality
Freely programmable timer and alarm with interrupt capability
Clock operating voltage: 1.1 V to 5.5 V
3 line SPI-bus with separate, but combinable data input and output
Serial interface at V
1 second or 1 minute interrupt output
Integrated oscillator load capacitors for C
Internal Power-On Reset (POR)
Open-drain interrupt and clock output pins
Programmable offset register for frequency adjustment
Time keeping application
Battery powered devices
Metering
High duration timers
Daily alarms
Low standby power applications
DD
1
= 1.6 V to 5.5 V
Real-Time Clock (RTC) and calendar optimized for low power
L
= 7 pF
Section
DD
19.
= 2.0 V and T
Product data sheet
amb
= 25 C

Related parts for PCF2123TS/1,112

PCF2123TS/1,112 Summary of contents

Page 1

PCF2123 SPI Real time clock/calendar Rev. 4 — 22 December 2010 1. General description The PCF2123 is a CMOS applications. Data is transferred serially via a Serial Peripheral Interface (SPI-bus) with a maximum data rate of 6.25 Mbit/s. An alarm ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name PCF2123TS/1 TSSOP14 PCF2123BS/1 HVQFN16 PCF2123U/10AA/1 PCF2123U/10 PCF2123U/12AA/1 PCF2123U/12AA PCF2123U/12HA/1 PCF2123U/12HA [1] Sawn 6 inch wafer on Film Frame Carrier (FFC) for 6 inch wafer, see [2] Sawn 6 inch wafer with gold bumps on Film Frame Carrier (FFC) for 8 inch wafer, see 5 ...

Page 3

... NXP Semiconductors 6. Block diagram OSCI C OSCILLATOR OSCI 32.768 kHz OSCO C OSCO MONITOR TEST POWER ON RESET WATCH DOG SDO SDI SPI INTERFACE SCL Fig 1. Block diagram of PCF2123 PCF2123 Product data sheet DIVIDER OFFSET FUNCTION 0Dh Offset_register TIMER FUNCTION 0Eh Timer_clkout 0Fh Countdown_timer ...

Page 4

... NXP Semiconductors 7. Pinning information 7.1 Pinning OSCI 1 OSCO 2 3 n.c. PCF2123 TEST 4 INT Top view. For mechanical details, see page 46. Fig 2. Pin configuration for TSSOP14 (PCF2123TS/1) Fig 4. PCF2123 Product data sheet CLKOUT 12 CLKOE 11 n.c. 10 SCL 9 SDI 8 SDO 001aai551 Figure 30 on Fig 3. ...

Page 5

... NXP Semiconductors 7.2 Pin description Table 3. Pin description Symbol Pin TSSOP14 HVQFN16 (PCF2123TS/1) (PCF2123BS/1) OSCI 1 16 OSCO 14, 15 TEST 4 2 INT [ SDO 8 8 SDI 9 9 SCL 10 10 CLKOE 12 11 CLKOUT [1] The die paddle (exposed pad) is wired to V [2] The substrate (rear side of the die) is wired to V ...

Page 6

... NXP Semiconductors 8. Functional description The PCF2123 contains 16 8-bit registers with an auto-incrementing address counter, an on-chip 32.768 kHz oscillator with two integrated load capacitors, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, and a 6.25 Mbit/s SPI-bus. An offset register allows fine tuning of the clock. ...

Page 7

... NXP Semiconductors I DD (nA) (1) I (2) Maximum value for R Fig 5. 8.1.2 Power consumptions with respect to timer mode Four source clocks are possible for the timer. The 4.096 kHz source clock will add the greatest part to the power consumption. The selection almost indistinguishable and add very little. ...

Page 8

... NXP Semiconductors 8.2 Register overview 16 registers are available. The time registers are encoded in the Binary Coded Decimal (BCD) format to simplify application use. Other registers are either bit-wise or standard binary. Table 4. Registers overview Bit positions labelled as - are not implemented and will return a 0 when read. The bit position labelled not implemented and will return when read ...

Page 9

... NXP Semiconductors 8.3 Control registers 8.3.1 Register Control_1 Table 5. Bit [1] Default value. [2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see PCF2123 Product data sheet Control_1 - control and status register 1 (address 00h) bit description Symbol Value Description [1] EXT_TEST 0 normal mode ...

Page 10

... NXP Semiconductors 8.3.1.1 Reset A reset is automatically generated at power-on. A reset can also be initiated with the software reset command generally recommended to make a software reset after power-on. A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see bit sequence is not correct, the software reset instruction will be ignored to protect the device from accidently being reset ...

Page 11

... NXP Semiconductors Table 6. Bits labeled as - are not implemented. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh PCF2123 Product data sheet ...

Page 12

... NXP Semiconductors 8.3.2 Register Control_2 Table 7. Bit [1] Default value. PCF2123 Product data sheet Control_2 - control and status register 2 (address 01h) bits description Symbol Value Description [ minute interrupt is disabled 1 minute interrupt is enabled [ second interrupt is disabled 1 second interrupt is enabled [1] MSF 0 no minute or second interrupt generated ...

Page 13

... NXP Semiconductors 8.4 Time and date function The majority of the registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the seconds in 8.4.1 Register Seconds Table 8. Bit [1] Default value. Table 9. Seconds value (decimal 8.4.1.1 OS flag ...

Page 14

... NXP Semiconductors V DD oscillation OS flag Fig 9. The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance. This time may be in the range of 200 depending on crystal type, temperature and supply voltage ...

Page 15

... NXP Semiconductors 8.4.4 Register Days Table 12. Bit [1] The PCF2123 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.4.5 Register Weekdays Table 13. Bit Table 14. [1] Day Sunday Monday Tuesday Wednesday ...

Page 16

... NXP Semiconductors Table 16. Month January February March April May June July August September October November December 8.4.7 Register Years Table 17. Bit 8.4.8 Setting and reading the time Figure 10 Fig 10. Data flow of the time function PCF2123 Product data sheet Month assignments in BCD format ...

Page 17

... NXP Semiconductors During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored ...

Page 18

... NXP Semiconductors 8.5 Alarm function When one or more of these registers are loaded with a valid minute, hour, day, or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information will be compared with the current minute, hour, day, and weekday. 8.5.1 Register Minute_alarm Table 18 ...

Page 19

... NXP Semiconductors 8.5.4 Register Weekday_alarm Table 21. Bit [1] Default value. 8.5.5 Alarm flag By clearing the MSB, AE_x (Alarm Enable), of one or more of the alarm registers the corresponding alarm condition(s) are active. When an alarm occurs, AF (register Control_2, see interrupt (INT). The AF is cleared using the interface. ...

Page 20

... NXP Semiconductors The generation of interrupts from the alarm function is controlled via bit AIE (register Control_2, see will remain set until cleared by the interface. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their AE_x bit logic 1 are ignored ...

Page 21

... NXP Semiconductors 8.6 Timer functions The countdown timer has four selectable source clocks allowing for countdown periods in the range from 244  min. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. For periods greater than 4 hours, the alarm function can be used ...

Page 22

... NXP Semiconductors INT when only MI enabled MSF when only MI enabled Fig 14. INT example for MI and SI Table 26. Minute interrupt (bit MI The minute and second flag (bit MSF) is set logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface ...

Page 23

... NXP Semiconductors 8.6.4 Countdown timer function The 8-bit countdown timer at address 0Fh is controlled by the register Timer_clkout at address 0Eh. The register Timer_clkout selects one of 4 source clock frequencies for the timer (4.096 kHz, 64 Hz, 1 Hz, or Table 28. CTD[1: [1] When not in use, CTD must be set to [2] Time periods can be affected by correction pulses ...

Page 24

... NXP Semiconductors therefore changing it without setting bit may result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the first period. The countdown value n will, however, be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated provided that this mode is enabled ...

Page 25

... NXP Semiconductors Three examples are given for clearing the flags. Clearing the flags is made by a write command, therefore bits and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. Table 30. Register Control_2 Table 31, appropriate flag. ...

Page 26

... NXP Semiconductors 8.7 Interrupt output An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits of register Control_2. Interrupts may be sourced from four places: second and minute timer, countdown timer, alarm function or offset function. With bit TI_TP, the timer generated interrupts can be configured to either generate a pulse or to follow the status of the interrupt flags (bits TF and MSF) ...

Page 27

... NXP Semiconductors 8.7.1 Minute and second interrupts The pulse generator for the minute and second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of If the MSF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. ...

Page 28

... NXP Semiconductors (1) Indicates normal duration of INT pulse (bit TI_TP = 1). Fig 18. Example of shortening the INT pulse by clearing the TF flag The timing shown for clearing bit TF in mode, i.e., when bit TI_TP = 0; INT may be shortened by setting bit TIE to logic 0. 8.7.3 Alarm interrupts The generation of interrupts from the alarm function is controlled via bit AIE (see If bit AIE is enabled, the INT pin follows the condition of bit AF ...

Page 29

... NXP Semiconductors 8.8 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] bits in the register Timer_clkout. Frequencies of 32.768 kHz (default) down can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. ...

Page 30

... NXP Semiconductors 8.9 Offset register The PCF2123 incorporates an offset register (address 0Dh) which can be used to implement several functions, such as: • Ageing adjustment • Temperature compensation • Accuracy tuning The offset is made once every two hours in the normal mode, or once every hour in the course mode ...

Page 31

... NXP Semiconductors Table 38. Correction value +1 or   3 : +59 or 59 +60 or 60 +61 or 61 +62 or 62 +63 or 63 64 [1] Example is given in a time range from 2:00 to 2:59. [2] Correction INT pulses are It is possible to monitor when correction pulses are applied. The correction interrupt enable mode (bit CIE) will generate a applied ...

Page 32

... NXP Semiconductors Table 39. Frequency (Hz) CLKOUT 32768 16384 8192 4096 2048 1024 1 Time source clock 4096 64 1  PCF2123 Product data sheet Effect of correction pulses All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 December 2010 PCF2123 SPI Real time clock/calendar ...

Page 33

... NXP Semiconductors 8.10 External clock test mode A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST in register Control_1. Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the signal applied to pin CLKOUT ...

Page 34

... NXP Semiconductors 8.11 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F thus ticks will be generated. The time circuits can then be set and will not increment until the STOP bit is released (see The STOP bit function will not affect the output of 32 ...

Page 35

... NXP Semiconductors Table 40. First increment of time circuits after STOP bit release [1] Bit Prescaler bits STOP Clock is running normally 0 01-0 0001 1101 0100 STOP bit is activated by user XX-0 0000 0000 0000 New time is set by user 1 XX-0 0000 0000 0000 STOP bit is released by user ...

Page 36

... NXP Semiconductors 8.12 3-line serial interface Data transfer to and from the device is made via a 3-wire SPI-bus (see data lines for input and output are split. The data input and output lines can be connected together to facilitate a bidirectional data bus. The chip enable signal is used to identify the transmitted data ...

Page 37

... NXP Semiconductors Table 42. Bit Figure 10 minutes. R SCL SDI CE address xx counter Fig 24. Serial bus write example In Figure are not connected together. For this configuration important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high I currents may result ...

Page 38

... NXP Semiconductors R SCL SDI SDO CE address xx counter Fig 25. Serial bus read example 8.12.1 Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface by setting pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will automatically clear the interface and allow the time counting circuits to continue counting ...

Page 39

... NXP Semiconductors The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. Each time the watchdog period is exceeded will be lost from the time counters. The watchdog will trigger between 1 s and 2 s after receiving a valid subaddress. ...

Page 40

... NXP Semiconductors 10. Limiting values Table 43. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot V ESD stg T amb [1] With respect to V [2] Pass level; Human Body Model (HBM) according to [3] Pass level; latch-up testing, according to [4] According to the NXP store and transport requirements (see stored at a temperature of +8  ...

Page 41

... NXP Semiconductors 11. Static characteristics Table 44. Static characteristics specified. Symbol Parameter Supplies V supply voltage DD I supply current DD Inputs V LOW-level input voltage IL V HIGH-level input voltage IH V input voltage I PCF2123 Product data sheet    + 32.768 kHz; quartz R amb osc Conditions for clock data integrity ...

Page 42

... NXP Semiconductors Table 44. Static characteristics specified. Symbol Parameter I input leakage current LI R pull-down resistance pd C input capacitance i Outputs V output voltage O V HIGH-level output voltage on pin SDO OH V LOW-level output voltage OL I HIGH-level output current OH I LOW-level output current OL I output leakage current ...

Page 43

... NXP Semiconductors 12. Dynamic characteristics Table 45. SPI-bus characteristics    +85 SS amb referenced to V and V with an input voltage swing Symbol Parameter Timing characteristics (see Figure f SCL clock frequency clk(SCL) t SCL time SCL t clock HIGH time clk(H) t clock LOW time clk(L) t rise time ...

Page 44

... NXP Semiconductors CE t su(CE) SCL WRITE SDI R/W SA2 Hi Z SDO READ SDI SDO Fig 28. SPI-bus timing PCF2123 Product data sheet 80% 20% RA0 t(SDI-SDO) All information provided in this document is subject to legal disclaimers. Rev. 4 — 22 December 2010 SPI Real time clock/calendar t w(CE) ...

Page 45

... NXP Semiconductors 13. Application information Fig 29. Typical application diagram PCF2123 Product data sheet 1 F supercapacitor 100 OSCI OSCO A 1 farad super capacitor combined with a low V supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks. ...

Page 46

... NXP Semiconductors 14. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 47

... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 48

... NXP Semiconductors 15. Bare die outline Wire bond die; 12 bonding pads; 1.492 x 1.449 x 0. DIMENSIONS (mm are the original dimensions) (1) (1) UNIT nom 0.20 1.492 1.449 Notes 1. Dimension includes saw lane 2. P and P : pad size and P : passivation opening 2 4 OUTLINE VERSION IEC PCF2123U/10 Fig 32 ...

Page 49

... NXP Semiconductors WLCSP12: wafer level chip size package; 12 bumps; 1.492 x 1.449 x 0. Dimensions (1) Unit max 0.018 mm nom 0.22 0.015 0.2 1.492 1.449 min 0.012 Note 1. Dimension includes saw lane and P : pad size and P : bump size Outline version IEC PCF2123U/12AA - - - Fig 33. Bare die outline of PCF2123U/12AA/1 ...

Page 50

... NXP Semiconductors WLCSP12: wafer level chip size package; 12 bumps; 1.492 x 1.449 x 0. Dimensions (1) Unit max 0.018 mm nom 0.17 0.015 0.15 1.492 1.449 min 0.012 Note 1. Dimension includes saw lane and P : pad size and P : bump size Outline version IEC PCF2123U/12HA - - - Fig 34. Bare die outline of PCF2123U/12HA/1 ...

Page 51

... NXP Semiconductors Table 47. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip; see Symbol SDO SDI SCL CLKOE CLKOUT V DD OSCI OSCO TEST INT Table 48. Coordinates x Location 693 Dimension 16 m [1] The x/y coordinates of the alignment mark location represent the position of the REF point (see with respect to the center (x the chip ...

Page 52

... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 17. Packing information 1.492 mm 1 1.449 mm ...

Page 53

... NXP Semiconductors metal frame ∅ 193.50 mm 214.50 mm Fig 37. Film Frame Carrier (FFC) for 6 inch wafer (PCF2123U/10AA/1) plastic frame ∅ 250 mm 276 mm Fig 38. Film Frame Carrier (FFC) for 8 inch wafer (PCF2123U/12AA/1 and PCF2123U/12HA/1) PCF2123 Product data sheet 214.50 mm 73.68 mm 71.79 mm straight edge ...

Page 54

... NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 55

... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 56

... NXP Semiconductors Fig 39. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 52. Acronym CMOS BCD ESD FFC HBM LSB MM MOS MSB MSL PCB RTC SMD SPI ...

Page 57

... NXP Semiconductors 20. References [1] AN10365 — Surface mount reflow soldering description [2] AN10706 — Handling bare die [3] AN10853 — Handling precautions of ESD sensitive devices [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [6] IPC/JEDEC J-STD-020D — ...

Page 58

... NXP Semiconductors 21. Revision history Table 53. Revision history Document ID Release date PCF2123 v.4 20101222 • Modifications: Adjusted bad die marking information PCF2123 v.3 20101005 PCF2123_2 20091204 PCF2123_1 20081119 PCF2123 Product data sheet Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet All information provided in this document is subject to legal disclaimers ...

Page 59

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 60

... If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die ...

Page 61

... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Low power operation . . . . . . . . . . . . . . . . . . . . 6 8.1.1 Power consumption with respect to quartz series resistance . . . . . . . . . . . . . . . . . . 6 8 ...

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