ISL1208IB8Z-TK Intersil, ISL1208IB8Z-TK Datasheet - Page 16
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ISL1208IB8Z-TK
Manufacturer Part Number
ISL1208IB8Z-TK
Description
IC RTC LP BATT BACKED SRAM 8SOIC
Manufacturer
Intersil
Type
Clock/Calendar/NVSRAMr
Datasheet
1.ISL1208IB8Z-TK.pdf
(24 pages)
Specifications of ISL1208IB8Z-TK
Memory Size
2B
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISL1208IB8Z-TKTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISL1208IB8Z-TK
Manufacturer:
STC
Quantity:
1 000
Part Number:
ISL1208IB8Z-TK
Manufacturer:
INTERSIL
Quantity:
20 000
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL1208 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1208 also responds with an ACK after receiving a Data
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
THE MASTER
THE ISL1208
16
START
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
START
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
S
T
A
R
T
1
FIGURE 14. BYTE WRITE SEQUENCE
IDENTIFICATION
1
1
0
BYTE
1
STABLE
1 1 1
DATA
ISL1208
0
WRITE
A
C
K
CHANGE
DATA
0 0 0 0
ADDRESS
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
BYTE
STABLE
DATA
A
C
K
8
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
S
T
O
P
September 12, 2008
FN8085.8