ISL1219IUZ Intersil, ISL1219IUZ Datasheet - Page 12

• Manufacturer Part Number: ISL1219IUZ
• Description: IC RTC LP BATT BACK SRAM 10MSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL1219IUZ

• Memory Size: 2B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 2 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: MSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register.
ADDR. SECTION
0Ch
0Dh
0Ah
0Bh
0Eh
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
Control
Stamp
Status
Alarm
User
Time
RTC
and
NAME
USR1
USR2
MNA
MOA
DWA
MOT
REG
DTR
SCA
HRA
MNT
HRT
ATR
DTA
SCT
DTT
YRT
MO
DW
INT
MN
HR
SC
DT
YR
SR
EV
Reserved
BMATR1
EVIENB
USR17
USR27
YRT23
EMNA
EMOA
EDWA
12
ESCA
EHRA
ARST
EDTA
YR23
MILT
MIL
IM
0
0
0
0
0
0
0
0
0
7
XTOSCB Reserved
EVBATB
BMATR0
AMN22
MNT22
ASC22
USR16
USR26
SCT22
YRT22
MN22
ALME
SC22
YR22
6
0
0
0
0
0
0
0
0
0
0
0
TABLE 5. REGISTER MEMORY MAP
LPMODE FOBATB
RTCHLT
AMN21
MNT21
ASC21
AHR21
ADT21
USR15
USR25
SCT21
HRT21
DTT21
YRT21
MN21
SC21
HR21
YR21
DT21
ATR5
5
0
0
0
0
0
AMO20
AMN20
AHR20
USR14
USR24
MNT20
MOT20
ISL1219
ASC20
ADT20
SCT20
HRT20
YRT20
WRTC
DTT20
MN20
MO20
EVEN
SC20
HR20
YR20
ATR4
DT20
4
0
0
BIT
AMO13
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
EHYS1
AMN13
AHR13
USR13
USR23
MNT13
MOT13
ASC13
ADT13
SCT13
HRT13
YRT13
DTT13
MN13
MO13
SC13
HR13
YR13
ATR3
DT13
EVT
FO3
3
0
0
AMN12
AMO12
ADW12
MOT12
EHYS0
AHR12
USR12
USR22
MNT12
ASC12
ADT12
SCT12
HRT12
DTT12
YRT12
MN12
MO12
DTR2
SC12
HR12
DT12
YR12
ATR2
DW2
ALM
FO2
2
ESMP1
AMO11
ADW11
AMN11
USR11
USR21
MNT11
MOT11
ASC11
AHR11
ADT11
SCT11
HRT11
YRT11
DTT11
MN11
MO11
DTR1
SC11
HR11
YR11
ATR1
DT11
DW1
BAT
FO1
1
ADW10
ESMP0
AMN10
AMO10
MNT10
MOT10
ASC10
AHR10
USR10
USR20
HRT10
ADT10
SCT10
DTT10
YRT10
MO10
MN10
HR10
RTCF
DTR0
SC10
DT10
YR10
ATR0
DW0
FO0
0
RANGE
00-59
00-59
00-59
00-59
0-59
0-59
0-23
1-31
1-12
0-99
0-23
1-31
1-12
0-23
1-31
1-12
0-99
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0-6
0-6
DEFAULT
July 15, 2010
00h
00h
00h
00h
00h
00h
00h
01h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FN6314.2