M41T82ZM6F STMicroelectronics, M41T82ZM6F Datasheet - Page 33

• Manufacturer Part Number: M41T82ZM6F
• Description: IC RTC SERIAL W/BATT SW 8-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T82ZM6F

• Memory Size: 32B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.38 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-7828-2; M41T82ZM6F

M41T82-M41T83
3.5
Note:
Figure 20. Crystal isolation example
1. Substrate pad should be tied to V
Setting the alarm clock registers
Codes not listed in the table default to the once-per-second mode to quickly alert the user of
an incorrect alarm setting. When the clock information matches the alarm clock settings
based on the match criteria defined by RPTx5–RPTx1 (x = 1 for alarm 1 or 2 for alarm 2),
the alarm flag, AFx, is set. Reading the flags register clears the alarm flags. A subsequent
read of the flags register is necessary to see that the value of the alarm flag has been reset
to 0.
M41T83 interrupts on alarm
In the M41T83, for alarm 1, setting the alarm interrupt enable, A1IE, allows an interrupt
output to be asserted upon AF1 being set provided that other configuration bits are set
accordingly (see
Likewise for alarm 2, with A2IE set, IRQ2 will be asserted upon AF2 going high. To disable
either of the alarms, write a 0 to the alarm date registers and to the RPTx5–RPTx1 bits.
If the address pointer is allowed to increment to the flag register address, or the last address
written is “Alarm Seconds,” the address pointer will increment to the flag address, and an
alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to
a different address.
Alarm IRQ outputs are de-asserted when the alarm flags are cleared by reading the flags
register (0Fh).
The IRQ1/FT/OUT pin can also be activated in the battery backup mode. This requires the
ABE bit (alarm in backup enable) to be set (see
conditions which apply). Once an interrupt is asserted in backup mode, it will remain true
until V
CC
is restored and a subsequent read of the flags register occurs.
Section 3.14
Doc ID 12578 Rev 12
SS
for more information on the IRQ/FT/OUT output).
.
Crystal
XI XO
V SS
Local Grounding
Plane (Layer 2)
Section 3.14.2: Backup mode
Clock operation
for additional
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