MAX19710ETN+ Maxim Integrated Products, MAX19710ETN+ Datasheet - Page 9

• Manufacturer Part Number: MAX19710ETN+
• Description: IC ANLG FRONT END 7.5MSPS 56TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19710ETN+

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 30mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
C
T
Note 1: Specifications from T
Note 2: Guaranteed by design and characterization.
Note 3: The minimum clock frequency (f
Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
Note 6: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output
A
DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0)
Input High Threshold
Input Low Threshold
Input Leakage
Input Capacitance
DIGITAL OUTPUTS (AD9–AD0, DOUT)
Output-Voltage Low
Output-Voltage High
Tri-State Leakage Current
Tri-State Output Capacitance
REFP
DD
= +25°C.) (Note 1)
= 3V, OV
= C
design and characterization.
(A
11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con-
version time (for no averaging, NAVG = 1) will be t
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tones.
signals using a sine-wave fit.
REFN
CLK
PARAMETER
DD
) is determined by f
= C
= 1.8V, internal reference (1.024V), C
COM
_______________________________________________________________________________________
= 0.33µF, C
A
= +25°C to +85°C guaranteed by production tests. Specifications at T
CLK
L
< 5pF on all aux-DAC outputs, T
and the chosen aux-ADC clock-divider value. The minimum aux-ADC A
SYMBOL
CLK
I
C
DC
V
V
DI
V
LEAK
V
OUT
INH
INL
OH
OL
) for the MAX19710 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequency
IN
IN
CLK, SCLK, DIN, CS/WAKE = OGND or
OV
DA9–DA0 = OV
DA9–DA0 = OGND
I
I
SINK
SOURCE
DD
L
10-Bit, 7.5Msps, Full-Duplex
≈ 10pF on all digital outputs, f
= 200µA
CONV
= 200µA
(max) = (12 x 1 x 128) / 1.5MHz = 1024µs.
CONDITIONS
DD
A
= T
MIN
to T
MAX
Analog Front-End
CLK
, unless otherwise noted. Typical values are at
= 7.5MHz (50% duty cycle), Rx ADC input
0.7 x OV
0.8 x OV
MIN
-1
-1
-5
-1
A
< +25°C guaranteed by
DD
DD
TYP
5
5
CLK
0.3 x OV
0.2 x OV
> 1.5MHz / 128 =
MAX
+1
+1
+5
+1
DD
DD
UNITS
µA
pF
µA
pF
V
V
V
V
9