MAX19710ETN+T Maxim Integrated Products, MAX19710ETN+T Datasheet - Page 8

IC ANLG FRNT END 56-TQFN

MAX19710ETN+T

Manufacturer Part Number
MAX19710ETN+T
Description
IC ANLG FRNT END 56-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX19710ETN+T

Number Of Bits
10
Number Of Channels
2
Power (watts)
30mW
Voltage - Supply, Analog
3V
Voltage - Supply, Digital
3V
Package / Case
56-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
C
T
8
Standby Wake-Up Time
Enable Time from Tx to Rx,
Fast Mode
E nab l e Ti m e fr om Rx to Tx,
Fast M od e
Enable Time from Tx to Rx,
Slow Mode
E nab l e Ti m e fr om Rx to Tx,
S l ow M od e
INTERNAL REFERENCE (V
Positive Reference
Negative Reference
Common-Mode Output Voltage
Maximum REFP/REFN/COM
Source Current
Maximum REFP/REFN/COM
Sink Current
Differential Reference Output
Differential Reference Temperature
Coefficient
BUFFERED EXTERNAL REFERENCE (external V
Reference Input Voltage
Differential Reference Output
Common-Mode Output Voltage
Maximum REFP/REFN/COM
Source Current
Maximum REFP/REFN/COM
Sink Current
REFIN Input Current
REFIN Input Resistance
A
REFP
(With CLK)
DD
= +25°C.) (Note 1)
_______________________________________________________________________________________
= 3V, OV
= C
REFN
PARAMETER
DD
= C
= 1.8V, internal reference (1.024V), C
COM
= 0.33µF, C
REFIN
= V
L
< 5pF on all aux-DAC outputs, T
t
t
t
t
t
SYMBOL
ENABLE,RX
ENABLE,RX
ENABLE,TX
ENABLE,TX
DD
WAKE,ST1
I
I
SOURCE
SOURCE
REFTC
V
V
V
V
I
V
I
REFIN
; V
SINK
SINK
COM
COM
DIFF
REF
REFP
, V
From standby to Rx mode, ADC settles to
within 1dB SINAD
From standby to Tx mode, DAC settles to
10 LSB error
From standby to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
V
V
V
V
REFIN
REFN
REFP
REFN
REFP
REFP
L
≈ 10pF on all digital outputs, f
, V
- V
- V
- V
- V
= 1.024V applied; V
COM
COM
REFN
REFN
COM
levels are generated internally)
CONDITIONS
A
= T
MIN
REFP
to T
MAX
, V
REFN
CLK
, unless otherwise noted. Typical values are at
= 7.5MHz (50% duty cycle), Rx ADC input
, V
COM
V
+0.490
- 0.15
DD
MIN
levels are generated internally)
/ 2
V
V
+0.512 +0.534
-0.256
0.256
1.024
0.512
TYP
22.2
22.2
DD
DD
±30
-0.7
500
7.5
0.1
0.1
7.3
5.2
2
2
2
2
/ 2
/ 2
V
+ 0.15
MAX
DD
/ 2
ppm/°C
UNITS
mA
mA
mA
mA
µA
µs
µs
µs
µs
µs
V
V
V
V
V
V
V

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