AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 11

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

THEORY OF OPERATION
To gain a general understanding of the AD9879, refer to the
block diagram of the device architecture in Figure 3. The
device consists of a transmit path, receive path, and auxiliary
functions, such as a DPLL, a Σ-Δ DAC, a serial control port,
and a cable amplifier interface.
TRANSMIT PATH
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a
12-bit current output DAC. The maximum output current of
the DAC is set by an external resistor. The Tx output PGA
provides additional transmit signal level control.
The transmit path interpolation filter provides an upsampling
factor of 16 with an output signal bandwidth as high as
5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS).
CA_PORT
RXIQ[3:0]
PROFILE
RXSYNC
TXSYNC
REFCLK
IF[11:0]
SPORT
MCLK
TXIQ
12
6
3
4
4
ASSEMBLER
DATA
INTERFACE
INTERFACE
RXPORT
PROFILE
SELECT
SERIAL
Q
I
CA
÷R
12
12
(f
IQ
IF
IQCLK
FIR LPF
)
4
4
÷4
AD9879
12
12
CIC LPF
MUX
MUX
4
4
(f
MCLK
Figure 3. Block Diagram
)
Rev. A | Page 11 of 32
CLAMP LEVEL
QUADRATURE
MODULATOR
DDS
(f
(f
÷4
÷8
÷2
÷2
OSCIN
OSCIN
COS
)
)
SIN
—
The transmit DAC resolution is 12 bits and can run at sampling
rates as high as 232 MSPS. Analog output scaling from 0.0 dB
to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
DATA ASSEMBLER
The AD9879 data path operates on two 12-bit words, the I and
Q components, which compose a complex symbol. The data
assembler builds the 24-bit complex symbols from four
consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The
nibbles are strobed synchronous to the master clock, MCLK,
into the data assembler. A high level on TxSYNC signals the
start of a transmit symbol. The first two nibbles of the symbol
form the I component, and the second two nibbles form the Q
component. Symbol components are assumed to be in twos
complement format. The timing of the interface is fully
described in the Transmit Timing section of this data sheet.
–
÷2
DAC GAIN CONTROL
SINC –1
SINC –1
BYPASS
Σ-∆ INPUT REGISTER
+
(f
SYSCLK
12
10
7
7
MUX
)
12
ADC
ADC
ADC
ADC
OSCIN × M
DAC
PLL
12
DAC
MUX
Σ-∆
(f
OSCIN
)
TX
FSADJ
FLAG1
I INPUT
IF10 INPUT
IF12 INPUT
XTAL
Σ-∆_OUT
Q INPUT
VIDEO INPUT
OSCIN
AD9879