AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 13

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

An internal PLL generates the DAC sampling frequency, f
by multiplying OSCIN frequency M times. The MCLK signal
(Pin 23), f
An external PLL loop filter (Pin 57) consisting of a series
resistor and ceramic capacitor (Figure 18, R1 = 1.3 kΩ,
C12 = 0.01 µF) is required for stability of the PLL. Also, a shield
surrounding these components is recommended to minimize
external noise coupling into the PLL’s voltage controlled
oscillator input (guard trace connected to AVDDPLL).
f
f
SYSCLK
MCLK
MCLK
= f
= f
OSCIN
OSCIN
, is derived by dividing f
× M/4
× M
(MSB) RXIQ(3)
(MSB) TXIQ(5)
(MSB) IF(11)
RXSYNC
TXSYNC
DRGND
RXIQ(2)
RXIQ(1)
RXIQ(0)
DRGND
DRVDD
DRVDD
TXIQ(4)
TXIQ(3)
TXIQ(2)
MCLK
DGND
DVDD
IF(10)
DNC
IF(9)
IF(8)
IF(7)
IF(6)
IF(5)
IF(4)
IF(3)
IF(2)
IF(1)
IF(0)
10
11
12
13
14
15
16
18
19
20
22
23
24
25
27
28
29
30
17
21
26
1
4
5
6
8
9
2
3
7
SYSCLK
PIN 1
by 4.
0.1µF
C1
Figure 4. Basic Connection Diagram
10µF
0.1µF
CP1
C2
SYSCLK
(Pins Down)
0.1µF
AD9879
TOP VIEW
C3
Rev. A | Page 13 of 32
(4)
(5)
,
0.1µF
C4
0.1µF
10µF
CP2
C5
Figure 3 shows that ADCs are either sampled directly by a low
jitter clock at OSCIN or by a clock that is derived from the PLL
output. Operating modes can be selected in Register 0x08.
Sampling the ADCs directly with the OSCIN clock requires
MCLK to be programmed to be twice the OSCIN frequency.
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9879 provides an auxiliary output clock on Pin 71,
REFCLK. The value of the MCLK divider bit field, R,
determines its output frequency as shown:
In its default setting (0x00 in Register 0x01), the REFCLK pin
provides a buffered output of f
0.1µF
C13
0.1µF
f
f
C6
REFCLK
REFCLK
4.02kΩ
R
= f
= f
SET
MCLK
OSCIN
80
77
76
75
72
71
70
69
68
67
66
65
63
62
61
59
58
56
54
53
52
51
79
78
74
73
64
60
57
55
/R, for R = 2 − 3
/R, for R = 0
DNC
I+
I–
DNC
DNC
DNC
AGNDIQ
AVDDIQ
DRVDD
REFCLK
DRGND
DGND Σ-∆
FLAG1
DVDD Σ-
CA_EN
CA_DATA
CA_CLK
DVDDOSC
OSCIN
XTAL
DGNDOSC
AGNDPLL
PLLFILT
AVDDPLL
DVDDPLL
DGNDPLL
AVDDTX
TX+
TX–
Σ-∆
_OUT
∆


GUARD TRACE
1.3kΩ
OSCIN
R1
20pF
20pF
C10
C11
0.01µF
.
C12
AD9879
(6)
(7)