AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 17

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

REGISTER 0x00—INITIALIZATION
Bits 0–4: OSCIN Multiplier
This register field is used to program the on-chip multiplier
(PLL) that generates the chip’s high frequency system clock
f
selected, as shown in Table 5.
Table 5.
ADC Clock Select
1, f
0, f
When using the AD9879 in systems where the Tx path and Rx
path do not operate simultaneously, the value of M can be
programmed from 1 to 31. The maximum f
236 MHz must be observed, whatever value is chosen for M.
When M is set to 1, the internal PLL is disabled and all internal
clocks are derived directly from OSCIN.
Bit 5: RESET
Writing a 1 to this bit resets the registers to their default values
and restarts the chip. The RESET bit always reads back 0. The
bits in Register 0x00 are not affected by this software reset. A
low level at the RESET pin, however, would force all registers,
including all bits in Register 0x00, to their default state.
Bit 6: SPI Bytes LSB First
Active high indicates SPI serial port access of instruction byte
and data registers are least significant bit (LSB) first. Default low
indicates most significant bit (MSB) first format.
Bit 7: SDIO Bidirectional
Active high configures the serial port as a three-signal port with
the SDIO pin used as a bidirectional input/output pin. Default
low indicates the serial port uses four signals with SDIO
configured as an input and SDO configured as an output.
REGISTER 0x01—CLOCK CONFIGURATION
Bits 0–5: MCLK/REFCLK Ratio
This bit field defines R, the ratio between the auxiliary clock
output, REFCLK and MCLK. R can be any integer number
between 2 and 63. At default zero (R = 0), REFCLK provides a
buffered version of the OSCIN clock signal.
Bit 7: PLL Lock Detect
When this bit is set low, the REFCLK pin functions in its default
mode and provides an output clock with frequency f
described above.
If this bit is set to 1, the REFCLK pin is configured to indicate
whether the PLL is locked to f
pin should be low-pass filtered with an RC filter of 1.0 kΩ and
0.1 µF. A low output on REFCLK indicates the PLL has achieved
lock with f
SYSCLK
OSCIN
MCLK
. The value of M depends on the ADC clocking mode
(PLL Derived)
OSCIN
.
OSCIN
. In this mode, the REFCLK
SYSCLK
rate of
MCLK
M
8
16
/R, as
Rev. A | Page 17 of 32
REGISTER 0x02—POWER-DOWN
Sections of the chip that are not used can be powered down
when the corresponding bits are set high. This register has a
default value of 0x00, with all sections active.
Bit 0: Power-Down IQ ADC
Active high powers down the IQ ADC.
Bit 1: Power-Down IQ and IF10 ADC Reference
Active high powers down the IQ and IF10 ADC reference.
Bit 2: Power-Down IF10 ADC
Active high powers down the IF10 ADC.
Bit 3: Power-Down IF12 ADC Reference
Active high powers down the 12-bit ADC reference.
Bit 4: Power-Down IF12 ADC
Active high powers down the IF12 ADC.
Bit 5: Power-Down Digital TX
Active high powers down the digital transmit section of the
chip, similar to the function of the PWRDN pin.
Bit 6: Power-Down DAC TX
Active high powers down the DAC.
Bit 7: Power-Down PLL
Active high powers down the OSCIN multiplier.
REGISTERS 0x03–0x04—Σ-∆ AND FLAG CONTROL
The Σ-Δ control word is 12 bits wide and split into MSB bits
[11:4] and LSB bits [3:0]. Changes to the Σ-Δ control words take
effect immediately for every MSB or LSB register write. Σ-Δ
output control words have a default value of 0. The control
words are in straight binary format with 0x000 corresponding
to the bottom of the scale and 0xFFF corresponding to the top
of the scale. See Figure 8 for details.
If the flag enable (Register 0x03, Bit 0) is set high, the
Σ-Δ_OUT pin maintains a fixed logic level determined
directly by the MSB of the Σ-Δ control word.
The FLAG1 pin assumes the logic level programmed into the
FLAG1 bit (Register 0x03, Bit 1).
REGISTER 0x07—VIDEO INPUT CONFIGURATION
Bits 0–6: Clamp Level Control Value
The 7-bit clamp level control value is used to set an offset to the
automatic clamp level control loop. The actual ADC output has
a clamp level offset equal to 16 times the clamp level control
value as shown:
Clamp Level Offset = Clamp Level Control Value × 16
AD9879
(9)