CS5550-ISZ Cirrus Logic Inc, CS5550-ISZ Datasheet
CS5550-ISZ
Specifications of CS5550-ISZ
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CS5550-ISZ Summary of contents
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... The CS5550 has on-chip functionality to facilitate offset and gain ± calibration. The CS5550 features a bi-directional serial interface for communication with a microcontroller. ORDERING INFORMATION: CS5550-IS CS5550-ISZ -40°C to +85°C, Lead-free RESET 4th Order ∆Σ Digital Modulator Filter 2nd Order ∆Σ Digital ...
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... SWITCHING CHARACTERISTICS .......................................................................................... 8 2.1 Theory of Operation ......................................................................................................... 10 2.1.1 High-Rate Digital Low-Pass Filters ..................................................................... 10 2.1.2 Digital Compensation Filters ............................................................................... 10 2.1.3 Gain and Offset Adjustment ................................................................................ 10 2.2 Performing Measurements ............................................................................................... 10 2.3 CS5550 Linearity Performance ........................................................................................ 10 3. FUNCTIONAL DESCRIPTION ............................................................................................... 11 3.1 Analog Inputs ................................................................................................................... 11 3.2 Voltage Reference ........................................................................................................... 11 3.3 Oscillator Characteristics ................................................................................................. 11 3.4 Calibration ........................................................................................................................ 12 3.4.1 Overview of Calibration Process ......................................................................... 12 3 ...
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... LIST OF FIGURES Figure 1. CS5550 Read and Write Timing Diagrams...................................................................... 9 Figure 2. Oscillator Connection..................................................................................................... 11 Figure 3. System Calibration of Gain. ........................................................................................... 12 Figure 4. System Calibration of Offset. ......................................................................................... 12 Figure 5. Example of Gain Calibration .......................................................................................... 13 Revision Date PP1 October 2003 PP2 August 2004 F1 March 2005 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. ...
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... VD+ - The positive digital supply relative to DGND. DGND - The common-mode potential of digital ground must be equal to or above the common-mode potential of AGND. VA+ - The positive analog supply relative to AGND. AGND - The analog ground pin must be at the lowest potential. CS5550 Crystal In Serial Data Input Test Output Test Output ...
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... THD 1 Both Gain Ranges -0.25 (50, 60 Hz) (Gain = 10 (Gain = 50) (Gain = 10) EII 1 (Gain = 50) (Gain = 10 (Gain = 50) (Note 1) VOS (Note 1) FSE {(AIN2+) - (AIN2-)} AIN 2 THD 2 -0.25 (50, 60 Hz) (Gain = 10 (Gain = 10) EII 2 (Gain = 10 (Note 1) VOS (Note 1) FSE CS5550 = 25°C. A Min Typ Max Unit nV/° 500 100 VA -115 ...
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... Definition for PSRR: VREFIN tied to VREFOUT, VA 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the + supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. Then the CS5550 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’ ...
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... out out Symbol V IH 0.6 VD+ XIN (VD+) - 0.5 SCLK and RESET 0.8 VD XIN SCLK and RESET (VD+) - 1.0 out out out Symbol VD+ VA+ AGND VREF T A CS5550 Min Typ Max Unit - - 0 1 0 ±1 ±10 µ ±10 µ Min Typ Max Unit ...
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... Symbol MCLK (Note 8) t rise SCLK Any Digital Output t fall SCLK Any Digital Output t ost SCLK Pulse Width High t 1 Pulse Width Low CS5550 Min Typ Max Unit 2.5 4.096 5 MHz 1.0 µ 100 µ 1.0 µ 100 µs ...
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... Figure 1. CS5550 Read and Write Timing Diagrams DS630F1 CS5550 9 ...
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... The signed output format is a two’s complement format, and the output data words represent a normalized value between -1 and +1. The unsigned data in the CS5550 output registers represent normalized values between 0 and 1. A register value of 1 represents the maxi- mum possible value ...
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... This linearity is guaranteed for all available full-scale input voltage ranges. Note that until the CS5550 is calibrated (see Cali- bration) the accuracy of the CS5550 is not guaran- teed to within 0.1%. But the linearity of any given ± sample of CS5550, before calibration, will be within ±0.1% of reading over the ranges specified, with respect to the input voltage levels required to cause full-scale readings in the FILT Registers ...
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... The maximum value that the gain register can attain is 4. Therefore, for either channel, if the voltage level of a gain calibration in- put signal is low enough that it causes the CS5550 to attempt to set either gain register higher than 4, the gain calibration result will be invalid and all CS5550 results obtained while performing A/D conversions will be invalid ...
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... Gain Calibration Sequence Based on the level of the positive DC calibration voltage applied across the “+’ and “-” inputs, the CS5550 determines the Gain Register value by av- eraging the Digital Output Register’s output signal values over one computation cycle (N samples) and then dividing this average into 1 ...
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... INT pulse will be at least one DCLK cycle (DCLK = MCLK / K). 3.6 PCB Layout The CS5550 should be placed entirely over an an- alog ground plane with both the AGND and DGND 14 pins of the device connected to the analog plane. Place the analog-digital plane split immediately ad- jacent to the digital portion of the chip ...
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... CS5550. Commands that write to a register must be followed by 3 bytes of register data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can execute before the original read is completed). This allows for “ ...
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... In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Waking up the CS5550 out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal. ...
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... Computed Filtered value for AIN2 2 Reserved † Reserved † Status Register Reserved Reserved Reserved † Reserved Reserved † Reserved † Reserved † Reserved † Reserved † Reserved † Mask Register Reserved † Control Register Reserved † Reserved † Reserved † CS5550 th SCLK. 17 ...
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... MCLK received after detecting a reset event. The internal register values are also set to their default values af- ter initial power-on of the device. The CS5550 will then assume its active state. (The term active state, CS5550 ...
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... Performing either of the following actions will insure that the CS5550 is op- erating in the active state: 1) Power on the CS5550. (Or if the device is al- ready powered on, recycle the power.) 2) Software Reset 3) Hardware Reset ...
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... Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be- tween 1 and 16. Note that a value of “0000” will set (not zero IMODE IINV iCPU K3 CS5550 gain DS630F1 ...
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... The Cycle Count Register value (denoted as ‘N’) determines the length of one computation cycle. During con- tinuous conversions, the computation cycle frequency is (MCLK/K)/(1024∗N) where MCLK is master clock input frequency (into XIN/XOUT pins clock divider value (as specified in the Configuration Register), and N is Cycle Count Register Value. DS630F1 - -17 ..... -16 ..... ..... CS5550 -18 -19 -20 -21 - -17 -18 -19 -20 - LSB ...
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... OR1, OR2 AIN Output Out of Range. Set when the magnitude of the calibrated output is too large or too -17 ..... -18 ..... and FILT CRDY OD2 OD1 CS5550 -18 -19 -20 -21 - -19 -20 -21 -22 - The results are in the range OR1 LSB -23 2 LSB -24 2 ...
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... Section 4.1, Commands). 5.8 Control Register Register Address Default** = 0x000000 INTOD 1 = Converts INT output to open drain configuration. NOCPU 1 = saves power by disabling the CPUCLK external drive pin. NOOSC 1 = saves power by disabling the crystal oscillator circuit. DS630F1 INTOD CS5550 NOCPU NOOSC 23 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5550 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5 ...