CS5550-ISZ Cirrus Logic Inc, CS5550-ISZ Datasheet - Page 17

• Manufacturer Part Number: CS5550-ISZ
• Description: IC ADC 2CH LOW-COST 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5550-ISZ

• Number Of Converters: 2
• Package / Case: 24-SSOP
• Number Of Bits: 2
• Sampling Rate (per Second): 4k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Architecture: Delta-Sigma
• Conversion Rate: 4 KSPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1119-5

4.1.7 Register Read/Write
The Read/Write command informs the state machine that a register access is required. During a read operation, the
addressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the
data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24
DS630F1
B7
0
W/R
RA[4:0]
Address
† These registers are for internal use only. For proper device operation, the user must not attempt to write
W/R
B6
0
1
2
3
2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
to these registers.
RA4
B5
0 = Read register
1 = Write register
Write/Read control
Register address bits (bits 1 through 5) of the read/write command.
RA[4-0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
RA3
B4
RA2
B3
Abbreviation
Config
AIN1
AIN1
AIN2
AIN2
Cycle Count
Res
OUT
OUT
Res
Res
FILT
FILT
Res
Res
Status
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Mask
Res
Ctrl
Res
Res
Res
RA1
1
2
1
2
DCoff
gn
DCoff
gn
B2
RA0
B1
Name/Description
Configuration Register
AIN1 Offset Register
AIN1 Gain Register
AIN2 Offset Register
AIN2 Gain Register
Number of A/D conversions used in one computation cycle (N)).
Reserved †
AIN1 Output Register
AIN2 Output Register
Reserved †
Reserved †
Computed Filtered value for AIN1
Computed Filtered value for AIN2
Reserved †
Reserved †
Status Register
Reserved
Reserved
Reserved †
Reserved
Reserved †
Reserved †
Reserved †
Reserved †
Reserved †
Reserved †
Mask Register
Reserved †
Control Register
Reserved †
Reserved †
Reserved †
B0
0
CS5550
th
SCLK.
17