ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 26

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

have a typical common mode voltage of 800mV when the
V
age can be increased to 1.2V by tying the V
higher common mode is required.
IMPORTANT NOTE: Tying the V
crease the differential LVDS output voltage by up to 40mV.
1.1.7 Power Down
The ADC08D500 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode, where the output pins hold the last con-
version before the PD pin went high and the device power
consumption is reduced to a minimal level. A high on the PDQ
pin will power down the "Q" channel and leave the "I" channel
active. There is no provision to power down the "I" channel
independently of the "Q" channel. Upon return to normal op-
eration, the pipeline will contain meaningless information.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
BG
SDR or DDR Clocking
DDR Clock Phase
SDR Data transitions with rising or
falling DCLK edge
LVDS output level
Power-On Calibration Delay
Full-Scale Range
Input Offset Adjust
Dual Edge Sampling Selection
Dual Edge Sampling Input Channel
Selection
DES Sampling Clock Adjustment
pin is unconnected and floating. This common mode volt-
Feature
BG
pin to V
Selected with pin 4
Not Selectable (0° Phase Only)
Selected with pin 4
Selected with pin 3
Delay Selected with pin 127
Options (650 mV
selected with pin 14. Selected range
applies to both channels.
Not possible
Enabled with pin 127
Only I-Channel Input can be used
The Clock Phase is adjusted
automatically
BG
A
pin to V
TABLE 2. Features and Modes
will also in-
Normal Control Mode
A
if a
P-P
or 870 mV
25
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state. Calibration will
function with the "Q" channel powered down, but that channel
will not be calibrated if PDQ is high. If the "Q" channel is sub-
sequently to be used, it is necessary to perform a calibration
after PDQ is brought low.
1.2 NORMAL/EXTENDED CONTROL
The ADC08D500 may be operated in one of two modes. In
the simpler "normal" control mode, the user affects available
configuration and control of the device through several control
pins. The "extended control mode" provides additional con-
figuration and control options through a serial interface and a
set of 8 registers. The two control modes are selected with
pin 14 (FSR/ECE: Extended Control Enable). The choice of
control modes is required to be a fixed selection and is not
intended to be switched dynamically while the device is op-
erational.
Table 2
by the control mode chosen.
P-P
)
shows how several of the device features are affected
Selected with DE bit in the Configuration
Register (1h).
Selected with DCP bit in the Configuration
Register (1h). See Section 1.4
Selected with the OE bit in the
Configuration Register (1h).
Selected with the OV bit in the
Configuration Register (1h).
Short delay only.
Up to 512 step adjustments over a
nominal range of 560 mV to 840 mV.
Separate range selected for I- and Q-
Channels. Selected using registers 3h
and Bh.
Separate ±45 mV adjustments in 512
steps for each channel using registers 2h
and Ah.
Enabled through DES Enable Register
(1h).
Either I- or Q-Channel input may be
sampled by both ADCs
Automatic Clock Phase control can be
selected by setting bit 14 in the DES
Enable register (Dh). The clock phase
can also be adjusted manually through
the Coarse & Fine registers Eh and Fh.
Extended Control Mode
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