LTC2259CUJ-14#PBF Linear Technology, LTC2259CUJ-14#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC2259CUJ-14#PBF
• Description: IC ADC 14-BIT 80MSPS 40-QFN
• Manufacturer: Linear Technology

Specifications of LTC2259CUJ-14#PBF

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 105mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50%(±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2261-14/LTC2260-14/LTC2259-14 can operate in
three digital output modes: full-rate CMOS, double-data
rate CMOS (to halve the number of output lines), or double-
data rate LVDS (to reduce digital noise in the system). The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
mode). Note that double-data rate CMOS cannot be selected
in the parallel programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 14 digital outputs (D0-D13),
overfl ow (OF), and the data output clocks (CLKOUT
CLKOUT
powered by OV
A/D core power and ground. OV
1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double-Data Rate CMOS Mode
In double-data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of data lines by seven, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 7 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11, D12_13), overfl ow (OF), and the data
output clocks (CLKOUT
levels. The outputs are powered by OV
are isolated from the A/D core power and ground. OV
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
–
) have CMOS output levels. The outputs are
DD
and OGND which are isolated from the
+
, CLKOUT
DD
can range from 1.1V to
–
) have CMOS output
DD
and OGND which
DD
+
,
When using double-data rate CMOS at high sample rates
the SNR will degrade slightly (see Typical Performance
Characteristics section). DDR CMOS is not recommended
for sample frequencies above 100MHz.
Double-Data Rate LVDS Mode
In double-data rate LVDS mode, two data bits are
multiplexed and output on each differential output pair.
There are 7 LVDS output pairs (D0_1
D12_13
(OF
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
isolated from the A/D core power and ground. In LVDS
mode, OV
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any refl ections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
Overfl ow Bit
The overfl ow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overfl ow bit has the same pipeline latency as the
data bits.
+
/OF
LTC2260-14/LTC2259-14
+
–
) and the data output clock (CLKOUT
/D12_13
DD
must be 1.8V.
–
) for the digital output data. Overfl ow
DD
LTC2261-14
and OGND which are
+
/D0_1
+
/CLKOUT
–
through
21
226114fa
–
)