LTC2259CUJ-16#PBF Linear Technology, LTC2259CUJ-16#PBF Datasheet
LTC2259CUJ-16#PBF
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LTC2259CUJ-16#PBF Summary of contents
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... An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 1. ...
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LTC2259-16 ABSOLUTE MAXIMUM RATINGS Supply Voltages ( ....................... –0. – Analog Input Voltage ( PAR/SER, SENSE) (Note 3) .......... –0. CS, + – Digital ...
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... ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL LTC2259CUJ-16#PBF LTC2259CUJ-16#TRPBF LTC2259IUJ-16#PBF LTC2259IUJ-16#TRPBF Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. ...
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LTC2259-16 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio INTERNAL REFERENCE CHARACTERISTICS ...
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DIGITAL INPUTS AND OUTPUTS temperature range, otherwise specifi cations are at T SYMBOL PARAMETER SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used) R Logic Low Output Resistance to GND OL I Logic High Output Leakage Current ...
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LTC2259-16 TIMING CHARACTERISTICS range, otherwise specifi cations are at T SYMBOL PARAMETER f Sampling Frequency S t ENC Low Time (Note ENC High Time (Note Sample-and-Hold Acquisition Delay AP Time Digital Data Outputs (CMOS ...
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TIMING DIAGRAMS ANALOG INPUT – ENC + ENC D0-D15 + CLKOUT – CLKOUT ANALOG INPUT – ENC + ENC D0_1 • • • D14_15 + CLKOUT – CLKOUT Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS ...
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LTC2259-16 TIMING DIAGRAMS ANALOG INPUT – ENC + ENC + D0_1 – D0_1 • • • + D14_15 – D14_15 + CLKOUT – CLKOUT SCK SDI R SDO HIGH IMPEDANCE CS SCK SDI A6 ...
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TYPICAL PERFORMANCE CHARACTERISTICS LTC2259-16: Integral Non-Linearity (INL –1 –2 –3 –4 0 16384 32768 49152 65536 OUTPUT CODE 225916 G01 LTC2259-16: 8k Point FFT 30MHz –1dBFS, 80Msps IN 0 –10 –20 –30 –40 ...
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LTC2259-16 TYPICAL PERFORMANCE CHARACTERISTICS LTC2259-16: SNR vs Input Frequency, –1dBFS, 2V Range, 80Msps 100 150 200 250 300 50 INPUT FREQUENCY (MHz) 225916 G08 LTC2259-16 Sample Rate, VDD ...
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PIN FUNCTIONS PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES + A (Pin 1): Positive Differential Analog Input. IN – A (Pin 2): Negative Differential Analog Input. IN GND (Pin 3, Exposed Pad Pin 41): ADC Power Ground. ...
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LTC2259-16 PIN FUNCTIONS FULL-RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND D15 (Pins 35, 36, 17-24, 29-34): Digital Outputs. D15 is the MSB the LSB. – CLKOUT (Pin ...
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FUNCTIONAL BLOCK DIAGRAM + A IN INPUT FIRST PIPELINED S/H ADC STAGE – 0.1μF V REF 1.25V REFERENCE 1μF RANGE SELECT REF SENSE BUF APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2259- low ...
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LTC2259-16 APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS Input Filtering If possible, there should lowpass fi lter right at the analog inputs. This lowpass fi lter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband ...
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APPLICATIONS INFORMATION Amplifi er Circuits Figure 7 shows the analog input being driven by a high speed differential amplifi er. The output of the amplifi AC-coupled to the A/D so the amplifi er’s output common mode voltage can ...
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LTC2259-16 APPLICATIONS INFORMATION Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are ...
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APPLICATIONS INFORMATION For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50%(±5%) ...
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LTC2259-16 APPLICATIONS INFORMATION Phase-Shifting the Output Clock In full-rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT + so the rising edge of CLKOUT can be used to latch the ...
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APPLICATIONS INFORMATION Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ...
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LTC2259-16 APPLICATIONS INFORMATION The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11, D13, D15). The alternate bit polarity mode is independent of the digital output randomizer—either, both or neither function ...
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APPLICATIONS INFORMATION Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a ...
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LTC2259-16 APPLICATIONS INFORMATION REGISTER A2: TIMING REGISTER (ADDRESS 02h Bits 7-4 Unused, Don’t Care Bits. Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (as shown in the timing diagrams Inverted ...
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APPLICATIONS INFORMATION REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h OUTTEST2 Bit 7-6 Unused, Don’t Care Bits. Bits 5-3 OUTTEST2:OUTTEST0 000 = Digital Output Test Patterns Off 001 = Digital Outputs = 0000 0000 0000 00XX 011 ...
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LTC2259-16 TYPICAL APPLICATIONS T2 MABAES0060 R9 10Ω • • R39 ANALOG INPUT 33.2Ω 1% R40 33.2Ω 1% R10 10Ω R15 100Ω C12 C13 0.1μF 1μF 24 LTC2259-16 Schematic SENSE C23 1μF R14 1k C51 4.7pF C17 1μF C19 0.1μF 40 ...
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TYPICAL APPLICATIONS Silkscreen Top Inner Layer 2 GND 225916 TA03 225916 TA04 LTC2259-16 Top Side 225916 TA04 Inner Layer 3 225916 TA06 225916f 25 ...
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LTC2259-16 TYPICAL APPLICATIONS Inner Layer 4 26 225916 TA07 Bottom Side 225916 TA09 Inner Layer 5 Power 225916 TA08 225916f ...
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... SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... CMOS/CMOS Outputs, 6mm × 6mm QFN Package www.linear.com ● DIGITAL OUTPUTS D1 D0 D15 D14 D13 D12 30 D11 29 D10 28 + CLKOUT 27 – CLKOUT C37 25 0.1μF OGND DIGITAL SDI SDO OUTPUTS 225916 TA10 LT 0310 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2010 0V DD 225916f ...