LTC2259CUJ-16#PBF Linear Technology, LTC2259CUJ-16#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC2259CUJ-16#PBF
• Description: IC ADC 16BIT 80MSPS 40QFN
• Manufacturer: Linear Technology

Specifications of LTC2259CUJ-16#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 80M
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 201mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2259-16
PIN FUNCTIONS
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
D0 to D15 (Pins 35, 36, 17-24, 29-34): Digital Outputs.
D15 is the MSB. D0 is the LSB.
CLKOUT
CLKOUT
normally transition at the same time as the falling edge
of CLKOUT
relative to the digital outputs by programming the mode
control registers.
DOUBLE-DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
D0_1 to D14_15 (Pins 36,18, 20, 22, 24, 30, 32, 34):
Double-Data Rate Digital Outputs. Two data bits are multi-
plexed onto each output pin. The even data bits (D0, D2, D4,
D6, D8, D10, D12, D14) appear when CLKOUT
odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear
when CLKOUT
CLKOUT
12
DD
DD
)
)
–
+
–
(Pin 28): Data Output Clock. The digital outputs
(Pin 27): Inverted Version of CLKOUT
(Pin 27): Inverted Version of CLKOUT
+
. The phase of CLKOUT
+
is high.
+
can also be delayed
+
is low. The
+
+
.
.
CLKOUT
normally transition at the same time as the falling and ris-
ing edges of CLKOUT
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
DOUBLE-DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1
19/20, 21/22, 23/24, 29/30, 31/32, 33/34): Double-Data
Rate Digital Outputs. Two data bits are multiplexed onto
each differential output pair. The even data bits (D0, D2,
D4, D6, D8, D10, D12, D14) appear when CLKOUT
The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15)
appear when CLKOUT
CLKOUT
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT
CLKOUT
by programming the mode control registers.
–
/D0_1
+
–
+
/CLKOUT
can also be delayed relative to the digital outputs
(Pin 28): Data Output Clock. The digital outputs
+
to D14_15
+
(Pins 27/28): Data Output Clock.
+
+
. The phase of CLKOUT
is high.
–
/D14_15
+
(Pins 35/36, 17/18,
+
. The phase of
+
can also
+
is low.
225916f