AD9265BCPZ-80 Analog Devices Inc, AD9265BCPZ-80 Datasheet - Page 33
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AD9265BCPZ-80
Manufacturer Part Number
AD9265BCPZ-80
Description
IC ADC 16BIT 80MSPS 48LFCSP
Manufacturer
Analog Devices Inc
Datasheet
1.AD9265BCPZ-125.pdf
(44 pages)
Specifications of AD9265BCPZ-80
Data Interface
Serial, SPI™
Number Of Bits
16
Sampling Rate (per Second)
80M
Number Of Converters
1
Power Dissipation (max)
258mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Resolution (bits)
16bit
Sampling Rate
80MSPS
Input Channel Type
Differential
Supply Voltage Range - Analog
1.7V To 1.9V
Supply Voltage Range - Digital
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9265BCPZ-80
Manufacturer:
ADI/亚德诺
Quantity:
20 000
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9265 includes built-in test features designed to enable
verification of the integrity of the part as well as facilitate board
level debugging. A BIST (built-in self-test) feature is included that
verifies the integrity of the digital datapath of the AD9265. Various
output test options are also provided to place predictable values on
the outputs of the AD9265.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9265 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value is placed in
Register 0x24 and Register 0x25.
Rev. A | Page 33 of 44
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the part configuration.
OUTPUT TEST MODES
The output test options are shown in Table 17. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
AD9265