LTC2439-1CGN Linear Technology, LTC2439-1CGN Datasheet - Page 18

• Manufacturer Part Number: LTC2439-1CGN
• Description: IC ADC 16BIT 16CH MCRPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2439-1CGN

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2439-1
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 19th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. If the device has not finished loading the
last input bit (A0 of SDI) by the time CS is pulled HIGH, the
address information is discarded and the previous ad-
dress is still kept. This is useful for aborting an invalid
conversion cycle, or synchronizing the start of a conver-
sion. If CS is pulled HIGH while the converter is driving
SCK LOW, the internal pull-up is not available to restore
SCK to a logic HIGH state. This will cause the device to exit
the internal serial clock mode on the next falling edge of
CS. This can be avoided by adding an external 10k pull-up
resistor to the SCK pin or by never pulling CS HIGH when
SCK is LOW.
Whenever SCK is LOW, the LTC2439-1’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
18
(INTERNAL)
SDO
SCK
SLEEP
SDI
CS
Hi-Z
> t
OUTPUT
DATA
EOCtest
BIT 0
EOC
U
CONVERSION
Hi-Z
DON’T CARE
TEST EOC
U
Hi-Z
SLEEP
(OPTIONAL)
TEST EOC
Figure 10. Internal Serial Clock, Reduced Data Output Length
SLEEP
Hi-Z
W
<t
EOCtest
(1)
BIT 18
EOC
BIT 17
“O”
REFERENCE
0.1V TO V
ANALOG
U
INPUTS
VOLTAGE
(0)
1µF
2.7V TO 5.5V
CC
BIT 16
•
•
•
•
•
•
SIG
11
12
21
28
10
9
1
8
EN
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
LTC2439-1
•
•
•
•
•
•
+
–
BIT 15
MSB
SGL
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2439-1’s internal pull-up remains disabled.
Hence, SCK remains LOW. On the next falling edge of CS,
the device is switched to the external SCK timing mode.
By adding an external 10k pull-up resistor to SCK, this pin
goes HIGH once the external driver goes Hi-Z. On the next
CS falling edge, the device will remain in the internal SCK
timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
SDO
GND
SCK
SDI
CS
F
O
17
15
18
19
20
BIT 14
16
ODD/
SIGN
DATA OUTPUT
4-WIRE
SPI INTERFACE
BIT 13
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
A2
50Hz/60Hz REJECTION
BIT 12
A1
BIT 11
A0
EOCtest
V
CC
10k
), the internal pull-up is
BIT 4
DON’T CARE
CONVERSION
Hi-Z
TEST EOC
24391 F09
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